Fast Recovery
Epitaxial Diode
(FRED) Module
Preliminary Data Sheet
V
RSM
V
800
1000
1200
V
RRM
V
800
1000
1200
Type
PSMD 30E/08
PSMD 30E/10
PSMD 30E/12
PSMD 30E
I
FAV
V
RRM
= 25 A
= 800-1200V
Symbol
I
FAV
I
FSM
Test Conditions
T
C
= 85°C
T
VJ
= 45°C
V
R
= 0
T
VJ
= T
VJM
V
R
= 0
t = 10 ms (50 Hz), sine
t = 8.3 ms (60 Hz), sine
t = 10 ms (50 Hz), sine
t = 8.3 ms (60 Hz), sine
t = 10 ms (50 Hz), sine
t = 8.3 ms (60 Hz), sine
t = 10 ms (50 Hz), sine
t = 8.3 ms (60 Hz), sine
Maximum Ratings
25
300
330
270
300
450
450
360
370
-40 ... + 150
150
-40 ... + 125
A
A
A
A
A
A
2
s
A
2
s
A
2
s
A
2
s
°C
°C
°C
V
∼
V
∼
Nm
Nm
g
∫
i
2
dt
T
VJ
= 45°C
V
R
= 0
T
VJ
= T
VJM
V
R
= 0
Features
•
Package with screw terminals
•
Isolation voltage 3000 V∼
•
Planar glasspassivated chips
•
Short recovery time
•
Low forward voltage drop
•
Short recovery behaviour
•
UL registered, E 148688
Applications
•
Inductive heating and melting
•
Free wheeling diode in converters
and motor control circuits
•
Uninterruptible power supplies
(UPS)
•
Ultrasonic cleaners and welders
T
VJ
T
VJM
T
stg
V
ISOL
M
d
Weight
50/60 HZ, RMS
I
ISOL
≤
1 mA
t = 1 min
t=1s
(M5)
(M5)
2500
3000
5
5
160
Mounting torque
Terminal connection torque
typ.
Advantages
•
High reliability circuit operation
•
Low voltage peaks for reduced
protection circuits
•
Low noise switching
•
Low losses
Package, style and outline
Dimensions in mm (1mm = 0.0394“)
Symbol
I
R
V
F
t
rr
V
TO
r
T
R
thJC
R
thJK
d
S
d
A
a
Test Conditions
V
R
= V
RRM
T
VJ
= 25°C
T
VJ
= 125°C
V
R
= 0,8•V
RRM
I
F
= 30 A
T
VJ
= 25°C
T
VJ
= 25°C, I
F
= 1A;
-di/dt = 100 A/µs; V
R
= 30V
For power-loss calculations only
T
VJ
= T
VJM
per diode; DC current
per module
per diode; DC current
per module
Creeping distance on surface
Creeping distance in air
Max. allowable acceleration
Characteristic Value
≤
≤
≤
750
7
2
100
1.5
12.5
1.0
0.5
1.2
0.6
10
9.4
50
µA
mA
V
ns
V
mΩ
K/W
K/W
K/W
K/W
mm
mm
m/s
2
POWERSEM GmbH, Walpersdorfer Str. 56
91126 D- Schwabach
Phone: 09122 - 9764-0 Fax.: 09122 - 9764-20
2005 POWERSEM reserves the right to change limits, test conditions and dimensions
FPGA/CPLD
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