AM29DL324GB90PCF datasheet, PDF

Datasheet> All Categories > storage> storage> AM29DL324GB90PCF

AM29DL324GB90PCF: DescriptionFlash, 2MX16, 90ns, PBGA64,; Categorystorage storage; File Size1MB，58 Pages; ManufacturerAMD; Websitehttp://www.amd.com; Environmental Compliance

Download Datasheet Parametric View All

AM29DL324GB90PCF Overview

Flash, 2MX16, 90ns, PBGA64,

AM29DL324GB90PCF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	AMD
package instruction	BGA, BGA64,8X8,40
Reach Compliance Code	unknown
Maximum access time	90 ns
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	S-PBGA-B64
memory density	33554432 bit
Memory IC Type	FLASH
memory width	16
Number of departments/size	8,63
Number of terminals	64
word count	2097152 words
character code	2000000
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA64,8X8,40
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Certification status	Not Qualified
ready/busy	YES
Department size	8K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.045 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE

Preview

Download Datasheet

View All

Am29DL32xG

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede AM29DL32xG as

the factory-recommended migration path. Please refer to each respective datasheets for specifica-

tions and ordering information. Availability of this document is retained for reference and historical

purposes only.”

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

25686

Revision

Amendment

Issue Date

June 7, 2005

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations ......................................................... 10

Unlock Bypass Command Sequence ........................................................26

Figure 3. Program Operation............................................................. 26

Chip Erase Command Sequence ...................................................................26

Sector Erase Command Sequence ................................................................ 27

Erase Suspend/Erase Resume Commands .................................................. 27

Figure 4. Erase Operation.................................................................. 28

Table 14. Command Definitions......................................................... 29

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ............................................................................................ 30

Figure 5. Data# Polling Algorithm...................................................... 30

Word/Byte Configuration .................................................................................10

Requirements for Reading Array Data ......................................................... 10

Writing Commands/Command Sequences .................................................. 11

Accelerated Program Operation ................................................................ 11

Autoselect Functions ...................................................................................... 11

Simultaneous Read/Write Operations

with Zero Latency ............................................................................................... 11

Standby Mode .........................................................................................................11

Automatic Sleep Mode ....................................................................................... 11

RESET#: Hardware Reset Pin ......................................................................... 12

Output Disable Mode ........................................................................................ 12

Table 2. Device Bank Divisions .......................................................... 12

Table 3. Top Boot Sector Addresses ................................................. 13

Table 4. Top Boot SecSi

Sector Addresses ...................................... 14

Table 5. Bottom Boot Sector Addresses ............................................. 15

Table 6. Bottom Boot SecSi

Sector Addresses ................................ 16

RY/BY#: Ready/Busy# .........................................................................................31

DQ6: Toggle Bit I ................................................................................................ 31

Figure 6. Toggle Bit Algorithm ........................................................... 31

DQ2: Toggle Bit II .............................................................................................. 32

Reading Toggle Bits DQ6/DQ2 ..................................................................... 32

DQ5: Exceeded Timing Limits ........................................................................ 32

DQ3: Sector Erase Timer ................................................................................ 32

Table 15. Write Operation Status .......................................................33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform............................ 34

Figure 8. Maximum Positive Overshoot Waveform.............................. 34

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents)................................................................ 36

Figure 10. Typical I

CC1

vs. Frequency ................................................. 36

Figure 11. Test Setup....................................................................... 37

Figure 12. Input Waveforms and Measurement Levels........................ 37

Autoselect Mode ..................................................................................................17

Table 7. Autoselect Codes, (High Voltage Method) ............................. 17

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 38

Sector/Sector Block Protection and Unprotection ...................................18

Table 8. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection ............................................................... 18

Table 9. Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection ............................................................... 18

Figure 13. Read Operation Timings.................................................... 38

Figure 14. Reset Timings................................................................... 39

Write Protect (WP#) ........................................................................................ 19

Temporary Sector Unprotect ......................................................................... 19

Figure 1. Temporary Sector Unprotect Operation ............................... 19

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms......................................................... 20

Word/Byte Configuration (BYTE#) ..............................................................40

Figure 15. BYTE# Timings for Read Operations................................... 40

Figure 16. BYTE# Timings for Write Operations.................................. 40

Erase and Program Operations .......................................................................41

Figure 17. Program Operation Timings...............................................

Figure 18. Accelerated Program Timing Diagram................................

Figure 19. Chip/Sector Erase Operation Timings.................................

Figure 20. Back-to-back Read/Write Cycle Timings.............................

Figure 21. Data# Polling Timings (During Embedded Algorithms)........

Figure 22. Toggle Bit Timings (During Embedded Algorithms) .............

Figure 23. DQ2 vs. DQ6....................................................................

SecSi

(Secured Silicon) Sector

Flash Memory Region ........................................................................................ 21

Factory Locked: SecSi Sector Programmed and Protected At the Fac-

tory ...................................................................................................................... 21

Customer Lockable: SecSi Sector NOT Programmed or Protected At

the Factory ........................................................................................................ 21

Hardware Data Protection .............................................................................. 21

Low VCC Write Inhibit ............................................................................... 22

Write Pulse “Glitch” Protection ............................................................... 22

Logical Inhibit .................................................................................................. 22

Power-Up Write Inhibit ............................................................................... 22

Temporary Sector Unprotect ........................................................................46

Figure 24. Temporary Sector Unprotect Timing Diagram..................... 46

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram. 47

Alternate CE# Controlled Erase and Program Operations .................48

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings............................................................................ 49

Common Flash Memory Interface (CFI) . . . . . . .22

Table 10. CFI Query Identification String............................................. 22

Table 11. System Interface String...................................................... 23

Table 12. Device Geometry Definition................................................. 23

Table 13. Primary Vendor-Specific Extended Query............................. 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . .24

Reading Array Data ........................................................................................... 24

Reset Command ..................................................................................................25

Autoselect Command Sequence ....................................................................25

Enter SecSi

Sector/Exit SecSi Sector

Command Sequence ..........................................................................................25

Byte/Word Program Command Sequence .................................................25

Erase And Programming Performance . . . . . . . . 50

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50

TSOP Pin and Fine-Pitch BGA Capacitance. . . . 50

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 51

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm .......... 51

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ..................................... 52

TS 048—Thin Small Outline Package .......................................................... 53

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 55

June 7, 2005

Am29DL32xG

Recommended Resources

JB35 module external circuit diagram

Baixue brand BD-140A refrigerator circuit

LT1185 application circuit diagram

Light control circuit with increasing and decreasing number of lights on

Nokia 3610 mobile phone troubleshooting actual color picture (1

Computer motherboard circuit diagram 820 1_45

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components