Philips Semiconductors
Product specification
20-bit buffer/line driver, non-inverting (3-State)
74ABT16827A
74ABTH16827A
FEATURES
•
Multiple V
CC
and GND pins minimize switching noise
•
Live insertion/extraction permitted
•
3-State output buffers
•
Power-up 3-State
•
74ABTH16827A incorporates bus-hold data inputs which
•
Output capability: +64mA/-32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
eliminate the need for external pull-up resistors to hold unused
inputs
DESCRIPTION
The 74ABT16827A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16827A 20-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NOR Output Enables (nOE1, nOE2) for maximum
control flexibility.
Two options are available, 74ABT16827A which does not have the
bus-hold feature and 74ABTH16827A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
PARAMETER
Propagation delay
nAx to nYx
Input capacitance
Output capacitance
Quiescent su ly current
supply
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5V
Outputs Low; V
CC
= 5.5V
TYPICAL
1.7
1.4
4
6
500
9
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16827A DL
74ABT16827A DGG
74ABTH16827A DL
74ABTH16827A DGG
NORTH AMERICA
BT16827A DL
BT16827A DGG
BH16827A DL
BH16827A DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 56,
28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
1OE0, 1OE1
2OE0, 2OE1
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active-Low)
Ground (0V)
Positive supply voltage
FUNCTION
1998 Feb 27
2
853-1824 19025
Philips Semiconductors
Product specification
20-bit buffer/line driver, non-inverting (3-State)
74ABT16827A
74ABTH16827A
LOGIC DIAGRAM
nA0
nA1
nA2
nA3
nA4
nA5
nA6
nA7
nA8
nA9
nOE0
nOE1
nY0
nY1
nY2
nY3
nY4
nY5
nY6
nY7
nY8
nY9
SH00013
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
mA
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
UNIT
V
mA
V
mA
V
mA
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
MIN
4.5
0
2.0
0.8
–32
64
10
+85
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1998 Feb 27
4
Philips Semiconductors
Product specification
20-bit buffer/line driver, non-inverting (3-State)
74ABT16827A
74ABTH16827A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
MIN
V
IK
V
OH
V
OL
I
I
Input clamp voltage
High-level output voltage
Low-level output voltage
Input leakage current
V
CC
= 4.5V; I
IK
= -18mA
V
CC
= 4.5V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 5.0V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= -32mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 5.5V; V
I
= 5.5V
I
I
Input leakage current
74ABTH16827A
V
CC
= 5.5V; V
I
= V
CC
or GND
V
CC
= 5.5V; V
I
= V
CC
V
CC
= 5.5V; V
I
= 0
I
HOLD
I
OFF
I
PU
/I
PD
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current
per input pin
2
Quiescent supply current
Bus Hold
B H ld current A inputs
5
t i
t
74ABTH16827A
Power-off leakage current
Power-up/down 3-State
output current
3
3-State output High current
3-State output Low current
Output High leakage
current
Output current
1
V
CC
= 4.5V; V
I
= 0.8V
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
V
CC
= 0.0V; V
O
= 4.5V; V
I
= 0V or 5.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or
V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–50
Control
pins
Data pins
4
35
–75
±800
±5.0
±5.0
1.0
–1.0
1.0
–70
0.5
9
0.5
0.2
±100
±50
10
–10
50
–180
1
19
1
1
–50
±100
±50
10
–10
50
–180
1
19
1
1
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
2.5
3.0
2.0
TYP
–0.9
2.9
3.4
2.4
0.42
±0.01
0.01
±0.01
0.01
–1
0.55
±1.0
1
±1
1
–3
35
–75
µA
MAX
–1.2
2.5
3.0
2.0
0.55
±1.0
1
±1
1
–5
T
amb
= -40°C
to +85°C
MIN
MAX
–1.2
V
V
V
V
V
µA
µA
µA
µA
µA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10% a
transition time of up to 100µsec is permitted.
4. Unused pins at V
CC
or GND.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
MIN
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
1998 Feb 27
Propagation delay
nAx to nYx
Output enable time
to High and Low level
Output disable time
from High and Low level
1
2
2
1.0
0.6
1.0
1.0
2.0
1.6
5
T
amb
= +25
o
C
V
CC
= +5.0V
TYP
1.7
1.4
3.0
3.0
3.2
2.4
MAX
2.4
2.0
4.1
4.0
4.3
3.2
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±0.5V
MIN
1.0
0.6
1.0
1.0
2.0
1.6
MAX
2.7
2.3
5.0
5.0
5.0
3.5
ns
ns
ns
UNIT
FPGA/CPLD
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