Preliminary Specifications
CMOS LSI
LE28CV1001DT/DTS-13/15
1M-Bit (128k × 8) Page Mode EEPROM
Features
Single 3.3-Volt Read and Write Operations
CMOS Flash EEPROM Technology
Page-write Endurance Cycles: 10
4
10 Years Data Retention
Low Power Consumption:
Active Current: 20 mA (Max.)
Standby Current: 15
µA
(Max.)
Fast Page-Write Operation
128 Bytes per Page
Page-Write Cycle: 5 ms (typical)
Complete Memory Rewrite: 5 sec. (typical)
Fast Access Time: 130ns / 150 ns
Latched Address and Data
Automatic Write Timing with Internal V
PP
Generation
End of Write Detection
Toggle Bit
DATA
Polling
Hardware and Software Data Protection
TTL I/O Compatibility
JEDEC Standard Byte-Wide EEPROM Pinouts
Packages Available
LE28CV1001DT : 32-pin TSOP (8mm × 20mm) Normal
LE28CV1001DTS: 32-pin TSOP (8mm × 14mm) Normal
Product Description
The LE28CV1001D is a 128K×8 CMOS page mode
EEPROM manufactured with SANYO's proprietary, high
performance CMOS Flash EEPROM Technology.
Breakthrough in EEPROM cell design and process
architecture attain better reliability and manufacturability
compared
with
conventional
approaches.
The
LE28CV1001D performs write in a 3.3-volt-only power
supply environment. Internal erase/program is transparent to
the user. The LE28CV1001D conforms to JEDEC standard
pinouts for byte-wide memories and is compatible with
existing industry standard EPROM, flash EPROM and
EEPROM pinouts.
Featuring high performance page write, the
LE28CV1001D provides an typical byte-write time of 39
µ
sec. The entire memory, i.e.128K bytes, can be written in as
little as 5 seconds using interface such as Toggle Bit and
DATA
Polling to indicate the completion of a write cycle.
To protect against inadvertent write, the LE28CV1001D has
on-chip hardware and software data protection schemes.
Designed, manufactured and tested for a wide spectrum of
applications, the LE28CV1001D is offered with page-write
endurance 10
4
cycles. Data retention is rated at greater than
10 years.
The LE28CV1001D is best suited for application that
require reprogrammable nonvolatile storage of program or
data memory for laptop computers, desktop computers,
medical instruments, laser printers, or copiers. For all system
applications, the LE28CV1001D significantly improves
performance and reliability, while lowering power
consumption, when compared with floppy disk or EPROM
approaches. In addtion, the EEPROM technology makes
convenient and economical updating of codes and control
programs on-line possible. The LE28CV1001D improves
flexibility while lowering the cost for program and
configuration strage applications such as operating systems,
BIOS, control programs, software I/O drivers, fonts, or
archives.
To meet high density, surface mount requirements, the
LE28CV1001D is offered in 32-pin TSOP package.
Device Operation
Both the high and medium endurance parts are identical
in functionality and features. The LE28CV1001D is
compatible to industry standard pinout and functionality.
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 2.10-January 10, 2001 -AY/ay-1/16
LE28CV1001DT/DTS-13/15
1M-Bit Page Mode EEPROM
Preliminary Specifications
A11
A9
A8
A13
A14
NC
WE
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
( Top
Viewl
)
Top
View
Figure 1: Pin Assignments for 32-pin TSOP
A16-A7
X-Address
Buffers
and Latches
Y-Address
Buffers
and Latches
1M Bit EEPROM
Cell Array
A6-A0
I/O Buffers
and Data Latches
CE
OE
WE
Control Logic
DQ7-DQ0
Figure2: Functional Block Diagram of LE28CV1001D
SANYO Electric Co., Ltd.
2/16
LE28CV1001DT/DTS-13/15
1M-Bit Page Mode EEPROM
Preliminary Specifications
Table 1: Pin Description
Symbol
Pin Name
A16-A0 Address Inputs
DQ7-DQ0 Data Input/Output
Functions
To provide memory address. Address are internally latched during write cycle.
To output data during read cycle and receive input data during write cycles. Data is internally
latched during a write cycle. The outputs are in tri-state when
OE
or
CE
is high.
To activate the device when
CE
is low. Deselects and puts the device to standby when
CE
is
high.
To activate the data output buffers.
OE
is active low.
To activate the write operation.
WE
is active low.
To provide 3.3V±0.3V.
Unconnected pins.
CE
OE
WE
V
CC
V
SS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Table 2: Operation Modes Selection
Mode
Read
Write
Standby
Write Inhibit
Product Identification
CE
OE
WE
DQ
Address
V
IL
V
IL
V
IL
X
X
V
IL
V
IL
V
IH
X
V
IL
X
V
IL
V
IH
V
IL
X
X
V
IH
V
IH
D
OUT
D
IN
High-Z
High-Z / D
OUT
High-Z / D
OUT
Manufacturer Code (BF)
Device Code (07)
A
IN
A
IN
X
X
X
A16-A1 = V
IL
, A9 = 12V, A0 = V
IL
A16-A1 = V
IL
, A9 = 12V, A0 = V
IH
Table 3: Software Data Protection Command Code
Byte Sequence
0
1
2
3
4
5
Write
Write
Write
Write
Write
Write
To Enable Protection
Address *
5555H
2AAAH
5555H
Data
AAH
55H
A0H
To Disable Protection
Address *
5555H
2AAAH
5555H
5555H
2AAAH
5555H
Data
AAH
55H
80H
AAH
55H
20H
* Address format A14-A0 (Hex.)
SANYO Electric Co., Ltd.
3/16
LE28CV1001DT/DTS-13/15
1M-Bit Page Mode EEPROM
Preliminary Specifications
Table 4: Software Product ID Entry Command Code and Exit Command Code
Byte Sequence
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
Address
5555H
2AAAH
5555H
5555H
2AAAH
5555H
Product ID Entry
Data
AAH
55H
80H
AAH
55H
60H
Address*
5555H
2AAAH
5555H
Product ID Exit
Data
AAH
55H
F0H
Notes for Software Product ID Command Code:
1. Command Code Address format: A14-A0 (Hex)
2. With A16-A1=0,
SANYO Manufacture Code = BFH is read with A0=0
LE28CV1001D Device Code =07H is read with A0=1
3. The device does not remain in Software product ID Mode if powered down.
SANYO Electric Co., Ltd.
4/16
LE28CV1001DT/DTS-13/15
1M-Bit Page Mode EEPROM
Preliminary Specifications
Read
The LE28CV1001D product read operation is controlled by
CE
and
OE.
The host must set both pins to the low level to
acquire the output data.
CE
is used for chip selection. When
CE
is at the high level, the chip will be in the unselected state and only
draw the standby current.
OE
is used for output control. The
output pins go to the high-impedance state when either
CE
or
OE
is high. See the timing waveforms (Figure 3) for details.
The page load period can continue indefinitely as long as host
continues to load data into the device within the 100µs byte load
cycle. The page that is loaded is determined by the page address of
the last byte loaded.
Detecting the Write Operation State
The LE28CV1001D product provides two functions for
detecting the completion of the write cycle. These functions are
used to optimize the system write cycle time. These functions are
based on detecting the states of the
DATA
Polling bit (DQ7) and
the toggle bit (DQ6).
Write
The write operation starts when both
CE
and
WE
are at the
low level. The write operation is executed in two stages. The first
stage is a byte load cycle in which the host writes to the
LE28CV1001D product internal page buffer. The second stage is
an internal programming cycle in which the data in the page buffer
is written to the nonvolatile memory cell array. In the byte-load
cycle, the address is latched on the falling edge of either
CE
or
WE
, whichever occurs later. The input data is latched on the rising
edge of either
CE
or
WE
, whichever occurs first. The internal
programming cycle starts if either
WE
or
CE
remains high for
200 µs (tBLCO). Once this programming cycle starts, the
operation continues until the programming operation is completely
done. This operation executes within 5ms (typical). Figures 4 and 5
show the
WE
and
CE
control write cycle timing diagrams, and
Figure 11 shows the flowchart for this operation.
In the page write operation, 128 bytes of data can be written to
the LE28CV1001D product internal page buffer before the internal
programming cycle. All the data in the page buffer is written to the
memory cell array during the 5m (typical) internal programming
cycle. Therefore the LE28CV1001D product page write function
can rewrite all memory cells in 5 seconds (typical). The host can
perform any other activities desired, such as moving data at other
locations within the system and preparing the data required for
next page write, during the period prior to the completion of the
internal programming cycle. In the given page write operation, all
the data bytes loaded into the page buffer must be for the same
page address specified by address lines A7 through A16. All data
was not explicitly loaded into the page buffer is set to FFH.
Figure 4 shows the page write cycle timing diagram. If the host
loads the second data byte into the page buffer within the 100µs
byte load cycle time (tBLC) after the first byte load cycle the
LE28CV1001D product stop in the page load cycle thus allowing
data to be loaded continuously . The page load cycle terminates if
additional data is not loaded into the internal page buffer within
200µs (tBLCO) after the previous byte load cycle, as in the case
where
WE
dose not switch from high to low after the last
WE
rising edge. The data in the page buffer can be rewritten in the next
byte load cycle.
DATA
Polling (DQ7)
The LE28CV1001D products output to DQ7 the inverse of the
last data loaded during the page and byte load cycles when the
internal programming cycle is in progress. The last data loaded will
be read from DQ7 when the internal programming cycle completes.
Figure 6 shows the
DATA
Polling cycle timing diagram and
Figure 12 shows the flowchart for this operation.
Toggle Bit (DQ6)
Data values of 0 and 1 are output alternately for DQ6, that is
DQ6 is toggled between 0and 1, during the internal programming
cycle. When the internal programming cycle completes this
toggling is stopped and the device becomes ready to execute the
next operation. Figure 7 shows the toggle bit timing diagram and
Figure 12 shows the flowchart for this operation.
Data Protection
Hardware Data Protection
Noise and glitch protection: The LE28CV1001D dose not
execute write operations for
WE
or
CE
pulses that are 15 ns or
shorter.
Power (V
CC
) on and cutoff detection: The programming
operation is disabled when V
CC
is 2.5 V or lower.
Write inhibit mode: Writing is disabled when
OE
is low and
either
CE
is high or
WE
is high. Use this function to prevent
writes from occurring when the power is being turned on or off.
Software Data Protection (SDP)
The LE28CV1001D implements the optional software data
protection function recognized by JEDEC. This function requires
that a 3-byte load operation to be performed before a write
operation data load. The 3-byte load sequence starts a page load
cycle without activating any write operation. Thus this is on
optimal protection scheme for unintended write cycles triggered by
noise associated with powering the chip on or off. Note that the
SANYO Electric Co., Ltd.
5/16
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