LE28C1001T-12 datasheet, PDF - EEWORLD Datasheet

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LE28C1001T-12: DescriptionIC,EEPROM,128KX8,CMOS,TSSOP,32PIN,PLASTIC; Categorystorage storage; File Size280KB，14 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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LE28C1001T-12 Overview

IC,EEPROM,128KX8,CMOS,TSSOP,32PIN,PLASTIC

LE28C1001T-12 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
package instruction	TSOP1-32
Reach Compliance Code	compliant
Maximum access time	120 ns
command user interface	NO
Data polling	YES
Durability	1000 Write/Erase Cycles
JESD-30 code	R-PDSO-G32
length	18.4 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP32,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
page size	128 words
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.00002 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	YES
width	8 mm
Maximum write cycle time (tWC)	10 ms

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Ordering number : EN*5129A

CMOS LSI

LE28C1001M, T-90/12/15

1MEG (131072 words

8 bits) Flash Memory

Preliminary

Overview

The LE28C1001M, T series ICs are 1 MEG flash memory

products that feature a 131072-word

8-bit organization

and 5 V single-voltage power supply operation. CMOS

peripheral circuits are adopted for high speed, low power

dissipation, and ease of use. A 128-byte page rewrite

function provides rapid data rewriting.

Package Dimensions

unit: mm

3205-SOP32

[LE28C1001M]

Features

• Highly reliable 2-layer polysilicon CMOS flash

EEPROM process

• Read and write operations using a 5 V single-voltage

power supply

• Fast access time: 90, 120, and 150 ns

• Low power dissipation

— Operating current (read): 30 mA (maximum)

— Standby current:

20 µA (maximum)

• Highly reliable read/write

— Erase/write cycles:

/10

cycles

— Data retention:

10 years

• Address and data latches

• Fast page rewrite operation

— 128 bytes per page

— Byte/page rewrite time: 5 ms (typical)

— Chip rewrite time:

5 s (typical)

• Automatic rewriting using internally generated Vpp

• Rewrite complete detection function

— Toggle bit

— Data polling

• Hardware and software data protection functions

• All inputs and outputs are TTL compatible.

• Pin assignment conforms to the JEDEC byte-wide

EEPROM standard.

• Package

SOP 32-pin (525 mil) plastic package : LE28C1001M

TSOP 32-pin (8

20 mm)plastic package : LE28C1001T

SANYO: SOP32

unit: mm

3224-TSOP32

[LE28C1001T]

SANYO: TSOP32 (TYPE-I)

These FLASH MEMORY products incorporate technology licensed Silicon Storage Technology, Inc.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

D3096HA (OT)/N3095HA (OT) No. 5129-1/14

LE28C1001M, T-90/12/15

Device Operation

This Sanyo 1 MEG flash memory allows electrical rewrites using a 5 V single-voltage power supply. The LE28C1001M,

T series products are pin and function compatible with the industry standards for this type of product.

Read

The LE28C1001M, T series read operations are controlled by CE and OE. The host must set both pins to the low level to

acquire the output data. CE is used for chip selection. When CE is at the high level, the chip will be in the unselected

state and only draw the standby current. OE is used for output control. The output pins go to the high-impedance state

when either CE or OE is high. See the timing waveforms (Figure 1) for details.

Page Write Operation

The write operation starts when both CE and WE are at the low level, and furthermore OE is at the high level. The write

operation is executed in two stages. The first stage is a byte load cycle in which the host writes to the LE28C1001M, T

series internal page buffers. The second stage is an internal programming cycle in which the data in the page buffer is

written to the nonvolatile memory cell array. In the byte load cycle, the address is latched on the falling edge of either

CE or WE, whichever occurs later. The input data is latched on the rising edge of either CE or WE, whichever occurs

first. The internal programming cycle starts if either WE or CE remains high for 200 µs (t

BLCO

). Once this programming

cycle starts, the operation continues until the programming operation is completely done. This operation executes within

5 ms (typical). Figures 2 and 3 show the WE and CE control write cycle timing diagrams, and Figure 10 shows the

flowchart for this operation.

In the page write operation, 128 bytes of data can be written to the LE28C1001M, T series internal page buffer before

the internal programming cycle. All the data in the page buffer is written to the memory cell array during the 5 ms

(typical) internal programming cycle. Therefore the LE28C1001M, T series page write function can rewrite all memory

cells in 5 seconds (typical). The host can perform any other activities desired, such as moving data at other locations

within the system and preparing the data required for the next page write, during the period prior to the completion of the

internal programming cycle. In a given page write operation, all the data bytes loaded into the page buffers must be for

the same page address specified by address lines A7 through A16. All data that was not explicitly loaded into the page

buffer is set to FFH.

Figure 2 shows the page write cycle timing diagram. If the host loads the second data byte into the page buffer within the

100 µs byte load cycle time (t

BLC

) after the first byte load cycle the LE28C1001M, T series stop in the page load cycle

thus allowing data to be loaded continuously. The page load cycle terminates if additional data is not loaded into the

internal page buffer within 200 µs (t

BLCO

) after the previous byte load cycle, as in the case where WE does not switch

from high to low after the last WE rising edge. The data in the page buffer can be rewritten in the next byte load cycle.

The page load period can continue indefinitely as long as the host continues to load data into the device within the 100 µs

byte load cycle. The page that is loaded is determined by the page address of the last byte loaded.

Detecting the Write Operation State

The LE28C1001M, T series products provide two functions for detecting the completion of the write cycle. These

functions are used to optimize the system write cycle time. These functions are based on detecting the states of the Data

polling bit (DQ7) and the toggle bit (DQ6).

Data Polling (DQ7)

The LE28C1001M, T series products output to DQ7 the inverse of the last data loaded during the page and byte load

cycles when the internal programming cycle is in progress. The last data loaded can be read from DQ7 when the internal

programming cycle completes. Figure 4 shows the Data polling cycle timing diagram and Figure 11 shows the flowchart

for this operation.

Toggle Bit (DQ6)

Data values of 0 and 1 are output alternately for DQ6, that is DQ6 is toggled between 0 and 1, during the internal

programming cycle. When the internal programming cycle completes this toggling is stopped and the device becomes

ready to execute the next operation. Figure 5 shows the toggle bit timing diagram and Figure 11 shows the flowchart for

this operation.

No. 5129-4/14

LE28C1001M, T-90/12/15

Data Protection

Hardware Data Protection

Noise and glitch protection: The LE28C1001M, T series do not execute write operations for WE or OE pulses that are 15

ns or shorter.

Power (V

) on and cutoff detection: The programming operation is disabled when V

is 2.5 V or lower.

Write inhibit mode: Writing is disabled when OE is low and either CE is high or WE is high. Use this function to prevent

writes from occurring when the power is being turned on or off.

Software Data Protection

The LE28C1001M, T series implement the optional software data protection function recognized by JEDEC. This

function requires a 3-byte load operation to be performed before a write operation data load. The 3-byte load sequence

starts a page load cycle without activating any write operation. Thus this is an optimal protection scheme for unintended

write cycles triggered by noise associated with powering the chip on or off. Note that the LE28C1001M, T series are

shipped with the software data protection function disabled.

The software data protection circuit is activated by executing a 3-byte byte load cycle in advance of the data sequence in

the page load cycle. (See Figure 6.) This causes the device to automatically enter data protection mode. After this, write

operations require a 3-byte byte load cycle to be executed in advance. A 6-byte write sequence is required to switch the

device out of this protection mode. Figure 7 shows the timing diagram. If a write operation is attempted in software

protection mode, all device functions are disabled for 200 µs. Figure 12 shows the flowchart for this operation.

Chip Erase

The LE28C1001M, T series provide a chip erase mode that erases all of the memory cell array and sets each bit to the 1

state. This mode can be effective when it is necessary to erase all data quickly.

5 V Single-Voltage Power Supply Software Chip Erase

The software chip erase mode operation is started by executing a specially defined 6-byte byte load sequence, similar to

page mode operation under software protection. After the load cycle is executed, the device enters an internal

programming cycle similar to the write cycle. Figure 8 shows the timing diagram and Figure 14 shows the flowchart for

this operation.

Product Identification

The device identification code is used for recognizing the device and its manufacturer. This mode can be used by

hardware and software. The hardware operating mode is used to recognize algorithms that match the device when an

external programming unit is used. Also, user systems can recognize the product number using software product

identification mode. Figure 13 shows the flowchart for this operation. The manufacturer and device codes are the same

in both modes.

No. 5129-5/14

LE28C1001T-12 Related Products

	LE28C1001T-12	LE28C1001M-90	LE28C1001M-15	LE28C1001M-12	LE28C1001T-90	LE28C1001T-15
Description	IC,EEPROM,128KX8,CMOS,TSSOP,32PIN,PLASTIC	IC,EEPROM,128KX8,CMOS,SOP,32PIN,PLASTIC	IC IC,EEPROM,128KX8,CMOS,SOP,32PIN,PLASTIC, Programmable ROM	IC,EEPROM,128KX8,CMOS,SOP,32PIN,PLASTIC	IC IC,EEPROM,128KX8,CMOS,TSSOP,32PIN,PLASTIC, Programmable ROM	IC,EEPROM,128KX8,CMOS,TSSOP,32PIN,PLASTIC
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
package instruction	TSOP1-32	SOP-32	SOP-32	SOP-32	TSOP1-32	TSOP1-32
Reach Compliance Code	compliant	not_compliant	compliant	compliant	compliant	compliant
Maximum access time	120 ns	90 ns	150 ns	120 ns	90 ns	150 ns
command user interface	NO	NO	NO	NO	NO	NO
Data polling	YES	YES	YES	YES	YES	YES
Durability	1000 Write/Erase Cycles	1000 Write/Erase Cycles	1000 Write/Erase Cycles	1000 Write/Erase Cycles	1000 Write/Erase Cycles	1000 Write/Erase Cycles
JESD-30 code	R-PDSO-G32	R-PDSO-G32	R-PDSO-G32	R-PDSO-G32	R-PDSO-G32	R-PDSO-G32
length	18.4 mm	20.7 mm	20.7 mm	20.7 mm	18.4 mm	18.4 mm
memory density	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit	1048576 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of terminals	32	32	32	32	32	32
word count	131072 words	131072 words	131072 words	131072 words	131072 words	131072 words
character code	128000	128000	128000	128000	128000	128000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128KX8	128KX8	128KX8	128KX8	128KX8	128KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP1	SOP	SOP	SOP	TSOP1	TSOP1
Encapsulate equivalent code	TSSOP32,.8,20	SOP32,.55	SOP32,.55	SOP32,.55	TSSOP32,.8,20	TSSOP32,.8,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
page size	128 words	128 words	128 words	128 words	128 words	128 words
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Programming voltage	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	3.1 mm	3.1 mm	3.1 mm	1.2 mm	1.2 mm
Maximum standby current	0.00002 A	0.00002 A	0.00002 A	0.00002 A	0.00002 A	0.00002 A
Maximum slew rate	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	1.27 mm	1.27 mm	1.27 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
switch bit	YES	YES	YES	YES	YES	YES
width	8 mm	11.2 mm	11.2 mm	11.2 mm	8 mm	8 mm
Maximum write cycle time (tWC)	10 ms	10 ms	10 ms	10 ms	10 ms	10 ms
Maker	ON Semiconductor	-	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor

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