PEEL16V8PL-15 datasheet, PDF - EEWORLD Datasheet

PEEL16V8PL-15: DescriptionEE PLD, 15ns, PAL-Type, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20; CategoryProgrammable logic devices Programmable logic; File Size633KB，10 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL16V8PL-15 Overview

EE PLD, 15ns, PAL-Type, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	DIP
package instruction	DIP, DIP20,.3
Contacts	20
Reach Compliance Code	unknown
Other features	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	45.5 MHz
JESD-30 code	R-PDIP-T20
JESD-609 code	e0
length	26.162 mm
Dedicated input times	8
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	64
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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