a
SUMMARY
Preliminary Technical Data
SHARC
®
Processor
Data Sheet Addendum
ADSP-21367/ADSP-21368/ADSP-21369
sample rate converter, precision clock generators, and
more. For complete ordering information, see
Ordering
Guide on Page 11.
At 400 MHz (2.5 ns) core instruction rate, the processors per-
form 2.4 GFLOPS/800 MMACS
Transfers between memory and core at a sustained
6.4G bytes/s bandwidth at 400 MHz core instruction rate
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bit of on-chip SRAM and 6M bit of on-
chip mask programmable ROM
400 MHz maximum core clock frequency
1.3 V core V
DD
/3.3 V I/O
Code compatible with all other members of the SHARC
family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audio-
centric peripherals such as the digital audio interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
GENERAL DESCRIPTION
This data sheet addendum introduces the 400 MHz ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors. This addendum pro-
vides the frequency benchmark, as well as ac and dc specifications that differ from the 333 MHz ADSP-21367/ADSP-21368/ADSP-21369
SHARC processors. All other specifications and timing data as well as package information for these devices can be found in the
ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data Sheet, Rev A. The products listed in the addendum are engineering
grade and have not been fully characterized. For complete ordering information, see the
Ordering Guide on Page 11.
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007
Analog Devices, Inc. All rights reserved.
ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum
TABLE OF CONTENTS
Summary ................................................................1
General Description ..................................................1
Specifications ...........................................................3
Operating Conditions .............................................3
Electrical Characteristics ..........................................3
Timing Specifications .............................................4
Output Drive Currents .......................................... 10
Capacitive Loading ............................................... 10
Ordering Guide ...................................................... 11
Preliminary Technical Data
Table 1
shows performance benchmarks for these devices.
Table 1. Processor Benchmarks (at 400 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/×)
Inverse Square Root
1
Speed (at 400 MHz)
23.2
μs
1.25 ns
5.0 ns
11.25 ns
20.0 ns
8.75 ns
13.5 ns
PERFORMANCE BENCHMARKS
The processors use two computational units to deliver a signifi-
cant performance increase over the previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21367/ADSP-
21368/ADSP-21369 processors achieve an instruction cycle
time of up to 2.5 ns at 400 MHz. With its SIMD computational
hardware, the processors can perform 2.4 GFLOPS running at
400 MHz.
Assumes two files in multichannel SIMD mode.
POWER SUPPLIES
The processors have separate power supply connections for the
internal (V
DDINT
), external (V
DDEXT
), and analog (A
VDD
/A
VSS
)
power supplies. The internal and analog supplies must meet the
1.3 V requirement for the 400 MHz device. The external supply
must meet the 3.3 V requirement. All external supply pins must
be connected to the same power supply.
Rev. PrA |
Page 2 of 12 | March 2007
Preliminary Technical Data
ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum
SPECIFICATIONS
OPERATING CONDITIONS
Parameter
1
V
DDINT
A
VDD
V
DDEXT
V
IH
2
V
IL
2
V
IH
_
CLKIN
3
V
IL
_
CLKIN
3
T
J
1
2
Description
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
High Level Input Voltage @ V
DDEXT
= max
Low Level Input Voltage @ V
DDEXT
= min
High Level Input Voltage @ V
DDEXT
= max
Low Level Input Voltage @ V
DDEXT
= min
Junction Temperature, 256-Ball SBGA @ T
AMBIENT
0°C to +70°C
Min
1.25
1.25
3.13
2.0
–0.5
1.74
–0.5
0
Max
1.35
1.35
3.47
V
DDEXT
+ 0.5
+0.8
V
DDEXT
+ 0.5
+1.1
+105
Unit
V
V
V
V
V
V
V
°C
Specifications subject to change without notice.
Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
ELECTRICAL CHARACTERISTICS
Parameter
1
V
OH
2
V
OL
2
I
IH
4, 5
I
IL
4, 6, 7
I
IHPD
6
I
ILPU
5
I
OZH
8, 9
I
OZL
8, 10
I
OZLPU
9
I
DD
-
INTYP
11
AI
DD
12
C
IN
13, 14
1
2
Description
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
High Level Input Current Pull-down
Low Level Input Current Pull-up
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current Pull-up
Supply Current (Internal)
Supply Current (Analog)
Input Capacitance
Test Conditions
@ V
DDEXT
= min, I
OH
= –1.0 mA
3
@ V
DDEXT
= min, I
OL
= 1.0 mA
3
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= 0 V
t
CCLK
= 2.5 ns, V
DDINT
= 1.3 V, 25°C
A
VDD
= max
f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 1.3 V
Min
2.4
Typ
Max
Unit
V
0.4
10
10
250
200
10
10
200
1.4
10
4.7
V
μA
μA
μA
μA
μA
μA
μA
A
mA
pF
Specifications subject to change without notice.
Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO,
CLKOUT.
3
See
Output Drive Currents on Page 10
for typical drive current capabilities.
4
Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.
5
Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.
6
Applies to input pins with internal pull-downs: IDx.
7
Applies to input pins with internal pull-ups disabled: ACK, RPBA.
8
Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.
9
Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.
10
Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10
11
See Engineer-to-Engineer Note 299 for further information.
12
Characterized, but not tested.
13
Applies to all signal pins.
14
Guaranteed, but not tested.
Rev. PrA |
Page 3 of 12 | March 2007
ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum
TIMING SPECIFICATIONS
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins. To determine switching
frequencies for the serial ports, divide down the internal clock,
using the programmable divider control of each port (DIVx for
the serial ports).
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
Preliminary Technical Data
Switching Characteristics
specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Rev. PrA |
Page 4 of 12 | March 2007
Preliminary Technical Data
Power-Up Sequencing
ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum
The timing requirements for processor startup are given in
Table 2.
Table 2. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
1
t
CLKRST
t
PLLRST
Switching Characteristic
t
CORERST
1
Min
RESET Low Before V
DDINT
/V
DDEXT
On
V
DDINT
On Before V
DDEXT
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
0
–50
0
10
2
20
4096t
CK
+ 2 t
CCLK
3, 4
Max
Unit
ns
ms
ms
μs
μs
+200
+200
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.3 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume
a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate
default states at all I/O pins.
4
The 4096 cycle count depends on t
srst
specification. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.
RESET
t
RSTVDD
VDDINT
t
IVDDEVDD
VDDEXT
t
CLKVDD
CLKIN
t
CLKRST
CLK_CFG1-0
t
PLLRST
RESETOUT
t
CORERST
Figure 1. Power-Up Sequencing
Rev. PrA |
Page 5 of 12 | March 2007
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