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ADSP-21368KBP-3A

Description
IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size821KB,12 Pages
ManufacturerADI
Websitehttps://www.analog.com
Download Datasheet Parametric Compare View All

ADSP-21368KBP-3A Overview

IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor

ADSP-21368KBP-3A Parametric

Parameter NameAttribute value
MakerADI
Parts packaging codeBGA
package instructionSBGA-256
Contacts256
Reach Compliance Codeunknown
Address bus width
barrel shifterNO
boundary scanNO
maximum clock frequency25 MHz
External data bus width
FormatFLOATING POINT
Internal bus architectureMULTIPLE
JESD-30 codeS-PBGA-B256
low power modeYES
Number of terminals256
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusNot Qualified
Maximum supply voltage1.35 V
Minimum supply voltage1.25 V
Nominal supply voltage1.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal locationBOTTOM
uPs/uCs/peripheral integrated circuit typeDIGITAL SIGNAL PROCESSOR, OTHER
a
SUMMARY
Preliminary Technical Data
SHARC
®
Processor
Data Sheet Addendum
ADSP-21367/ADSP-21368/ADSP-21369
sample rate converter, precision clock generators, and
more. For complete ordering information, see
Ordering
Guide on Page 11.
At 400 MHz (2.5 ns) core instruction rate, the processors per-
form 2.4 GFLOPS/800 MMACS
Transfers between memory and core at a sustained
6.4G bytes/s bandwidth at 400 MHz core instruction rate
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bit of on-chip SRAM and 6M bit of on-
chip mask programmable ROM
400 MHz maximum core clock frequency
1.3 V core V
DD
/3.3 V I/O
Code compatible with all other members of the SHARC
family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audio-
centric peripherals such as the digital audio interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
GENERAL DESCRIPTION
This data sheet addendum introduces the 400 MHz ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors. This addendum pro-
vides the frequency benchmark, as well as ac and dc specifications that differ from the 333 MHz ADSP-21367/ADSP-21368/ADSP-21369
SHARC processors. All other specifications and timing data as well as package information for these devices can be found in the
ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data Sheet, Rev A. The products listed in the addendum are engineering
grade and have not been fully characterized. For complete ordering information, see the
Ordering Guide on Page 11.
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007
Analog Devices, Inc. All rights reserved.

ADSP-21368KBP-3A Related Products

ADSP-21368KBP-3A ADSP-21369KBP-3A
Description IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor
Maker ADI ADI
Parts packaging code BGA BGA
package instruction SBGA-256 SBGA-256
Contacts 256 256
Reach Compliance Code unknown unknown
barrel shifter NO NO
boundary scan NO NO
maximum clock frequency 25 MHz 25 MHz
Format FLOATING POINT FLOATING POINT
Internal bus architecture MULTIPLE MULTIPLE
JESD-30 code S-PBGA-B256 S-PBGA-B256
low power mode YES YES
Number of terminals 256 256
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code BGA BGA
Package shape SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY
Certification status Not Qualified Not Qualified
Maximum supply voltage 1.35 V 1.35 V
Minimum supply voltage 1.25 V 1.25 V
Nominal supply voltage 1.3 V 1.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal form BALL BALL
Terminal location BOTTOM BOTTOM
uPs/uCs/peripheral integrated circuit type DIGITAL SIGNAL PROCESSOR, OTHER DIGITAL SIGNAL PROCESSOR, OTHER
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