TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators for PC Chipsets
with Power Good
BD3512MUV
(3A)
●
Description
The BD3512MUV ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal
performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to
minimize the input-to-output voltage differential to the ON resistance (R
ON
=100mΩ) level. By lowering the dropout voltage in
this way, the regulator realizes high current output (Iomax=3.0A) with reduced conversion loss, and thereby obviates the
switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3512MUV is designed to enable
significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage
configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up,
which can be programmed to whatever power supply sequence is required.
●
Features
1) Internal high-precision reference voltage circuit (0.65V±1%)
2) Built-in VCC undervoltage lockout circuit (VCC=3.80V)
3) NRCS (soft start) function reduces the magnitude of in-rush current
4) Internal Nch MOSFET driver offers low ON resistance (65mΩ typ)
5) Built-in current limit circuit (3.0A min)
6) Built-in thermal shutdown (TSD) circuit (Timer latch)
7) Variable output (0.65½2.7V)
8) High-power package VQFN020V4040 : 4.0×4.0×1.0(mm)
9) Tracking function
●
Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
Oct. 2008
●Absolute
maximum ratings (Ta=25℃)
Parameter
Input Voltage 1
Input Voltage 2
Input Voltage 3
Input Voltage 4
Maximum Output Current
Enable Input Voltage
PGOOD Input Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Power Dissipation 4
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Symbol
VCC
VIN
VCC
VD
IO
Ven
V
PGOOD
Pd1
Pd2
Pd3
Pd4
Topr
Tstg
Tjmax
Limit
6.0 *
6.0 *
1
6.0 *
1
1
3 *
1
6.0
6.0
0.34
*2
0.70
*3
1.21
*4
3.56
*5
-10½+100
-55½+125
+150
1
Unit
V
V
V
V
A
V
V
W
W
W
W
℃
℃
℃
*
1
Should not exceed Pd.
*
2
Reduced by 2.7mW/℃ for each increase in Ta≧25℃(no heat sink)
*
3
Reduced by 5.6mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.)
:No substrate surface copper foil area.
*
4
Reduced by 9.7mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.)
:4 layers, substrate surface copper foil area 10.29mm
2
.
5
* Reduced by 28.5mW for each increase in Ta of 1℃ over 25℃. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB.)
:4 layers, substrate surface copper foil area 5505mm
2
.
●Operating
Voltage (Ta=25℃)
Parameter
Input Voltage 1
Input Voltage 2
Input Voltage 3
Output Voltage Setting Range
Enable Input Voltage
*6
Symbol
VCC
VIN
VCC
Vo
Ven
Min.
4.3
0.7
4.5
VFB
-0.3
Max.
5.5
VCC-1 *
6
5.5
2.7
5.5
Unit
V
V
V
V
V
VCC and VIN do not have to be implemented in the order listed.
★This
product is not designed for use in radioactive environments.
2/16
●Electrical
Characteristics (Unless otherwise specified, Ta=25℃, Vcc=5V, Ven=3V, VIN=1.7V, R1=3.9KΩ, R2=3.3KΩ)
Limit
Parameter
Symbol
Unit
Condition
Min.
Typ.
Max.
Bias Current
Icc
-
1.4
2.2
mA
VCC Shutdown Mode Current
IST
-
0
10
uA
Ven=0V
Maximum Output Current
Io
3.0
-
-
A
Output Voltage Temperature
Tcvo
-
0.01
-
%/℃
Coefficient
Feedback Voltage 1
VFB1
0.643
0.650
0.657
V
Io=0 to 3A
Feedback Voltage 2
VFB2
0.637
0.650
0.663
V
Tj=-10 to 100℃
Line Regulation 1
Reg.l1
-
0.1
0.5
%/V Vcc=4.3V to 5.5V
Line Regulation 2
Reg.l2
-
0.1
0.5
%/V VIN=1.5V to 3.3V
Load Regulation
Reg.L
-
0.5
10
mV
Io=0 to 3A
Io=1A,VIN=1.2V
Minimum dropout voltage
dVo
-
65
100
mV
Standby Discharge Current
[ENABLE]
Enable Pin
Input Voltage High
Enable Pin
Input Voltage Low
Enable Input Bias Current
[FEEDBACK]
Feedback Pin Bias Current
[NRCS]
NRCS Charge Current
NRCS Standby Voltage
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCC Undervoltage Lockout
Hysteresis Voltage
VD Undervoltage Lockout
Threshold Voltage
[SCP]
SCP Startup Voltage
SCP Threshold Voltage
SCP Charge Current
SCP Standby Voltage
[PGOOD]
Low-side Threshold Voltage
High-side Threshold Voltage
PGDLY Charge Current
Ron
t
pgdly
=
C(pF)×1.23
I
pgdly
(μA)
Iden
1
-
-
mA
Ven=0V, Vo=1V
Enhi
Enlow
Ien
IFB
Inrcs
VSTB
2
-0.2
-
-100
14
-
-
-
6
0
20
0
-
0.8
10
100
26
50
V
V
uA
nA
uA
mV
Vnrcs=0.5V
Ven=0V
Ven=3V
VccUVLO
Vcchys
V
D
UVLO
3.5
100
V
REF
×
0.6
V
o
×0.3
1.05
1.4
-
3.8
160
V
REF
×
0.7
V
o
×0.4
1.15
2
-
4.1
220
V
REF
×
0.8
V
o
×0.5
1.25
2.6
50
V
mV
V
Vcc:Sweep-up
Vcc:Sweep-down
V
D
:Sweep-up
V
OSCP
V
SCPTH
I
SCP
V
SCPSTBY
V
THPGL
V
THPGH
Ipgdly
R
PG
V
V
μA
mV
V
V
μA
kΩ
V
o
×0.87
V
o
×0.9
V
o
×0.93
V
o
×1.07
V
o
×1.1
V
o
×1.13
1.4
2.0
2.6
-
0.1
-
※
※PGOOD
delay time is determined as in formula below.
(μsec)
3/16
●Reference
Data
Vo
50mV/div
Vo
50mV/div
Vo
50mV/div
Io
1A/div
3.0A
Io
1A/div
3.0A
Io
1A/div
3.0A
Io=0A→3A/3μsec
T(10μsec/div)
Io=0A→3A/3μsec
T(4μsec/div)
Io=0A→3A/3μsec
T(4μsec/div)
Fig.1 Transient Response
(0→3A)
Co=22μF, Cfb=1000pF
Fig.2 Transient Response
(0→3A)
Co=100μF
Fig.3 Transient Response
(0→3A)
Co=100μF, Cfb=1000pF
Vo
50mV/div
Vo
50mV/div
Vo
50mV/div
Io
1A/div
3.0A
Io
1A/div
3.0A
Io
1A/div
3.0A
Io=3A→0A/3μsec
T(40μsec/div)
Io=3A→0A/3μsec
T(100μsec/div)
Io=3A→0A/3μsec
T(100μsec/div)
Fig.4 Transient Response
(3→0A)
Co=22μF, Cfb=1000pF
Fig.5 Transient Response
(3→0A)
Co=100μF
Fig.6 Transient Response
(3→0A)
Co=100μF, Cfb=1000pF
Ven
2V/div
Ven
2V/div
VNRCS
1V/div
VCC
5V/div
Ven
2V/div
VIN
2V/div
Vo
1V/div
T(2msec/div)
VCC→VIN→Ven
VNRCS
1V/div
Vo
500mV/div
Vo
500mV/div
T(100μsec/div)
Fig.7 Waveform at output start
Fig.8 Waveform at output OFF
Fig.9 Input sequence
VCC
5V/div
Ven
2V/div
VIN
2V/div
Vo
1V/div
VIN→VCC→Ven
VCC
5V/div
Ven
2V/div
VIN
2V/div
Vo
1V/div
Ven→VCC→VIN
VCC
5V/div
Ven
2V/div
VIN
2V/div
Vo
1V/div
VCC→Ven→VIN
Fig.10 Input sequence
Fig.11 Input sequence
Fig.12 Input sequence
4/16
●Reference
Data
1.23
VCC
VCC
1.22
1.21
Ven
Ven
Vo [V]
1.20
VIN
VIN
1.19
1.18
Vo
VIN→Ven→VCC
Vo
1.17
Ven→VIN→VCC
-50
-25
0
25
50
Tj [℃]
75
100
125
150
Fig.13 Input sequence
Fig.14 Input sequence
Fig.15 Tj-Vo
2.0
1.9
1.8
1.7
5.0
4.5
4.0
3.5
50
45
40
35
I
INSTB
[μ A]
ISTB [μA]
1.6
Icc [mA]
1.5
1.4
1.3
1.2
1.1
1.0
-50
-25
0
25
50
Tj [℃]
75
100
125
150
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50
-25
0
25
50
75
100
125
150
30
25
20
15
10
5
0
-50
-25
0
25
50
75
100
125
150
Tj [℃]
Tj [℃]
Fig.16 Tj-ICC
Fig.17 Tj-ISTB
Fig.18 Tj-IINSTB
24
10
9
80
70
60
22
8
20
I
NRCS
[μA]
IEN [μA]
7
6
5
4
3
50
18
RON[mΩ]
-50
-25
0
25
50
75
100
125
150
40
30
20
16
14
2
1
10
0
-50
-25
0
25
50
75
100
125
150
12
-50
-25
0
25
50
Tj [℃]
75
100
125
150
0
Tj [℃]
Tj [℃]
Fig.19 Tj-INRCS
Fig.20 Tj-IEN
Fig.21 Tj-RON
(VCC=5V/VO=1.2V)
80
70
60
50
Vo=2.5V
45
RON [mΩ ]
50
40
30
R
ON
[mΩ]
Vo=1.8V
Vo=1.7V
Vo=1.5V
Vo=1.2V
40
20
10
0
-50
-25
0
25
50
75
100
125
150
35
3
5
7
Tj [℃]
Vcc [V]
Fig.22 Tj-RON
(VCC=5V/VO=1.5V)
Fig.23 VCC-RON
5/16
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