Hi-performance Regulator IC Series for PCs
Termination Regulators
for DDR-SDRAMs
BD3539FVM,BD3539NUX
No.09030EAT24
Description
BD3539FVM/NUX is a termination regulator compatible with JEDEC DDR1-SDRAM, DDR2-SDRAM, DDR3-SDRAM which
functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to
1A respectively. A built-in high-speed OP-AMP specially designed offers an excellent transient response. Requires 3.3
volts (DDR2, DDR3) or 5.0 volts (DDR1, DDR2, DDR3) as a bias power supply to drive the N-channel MOSFET. Has an
independent reference voltage input pin (VDDQ) and an independent feedback pin (VTTS) to maintain the accuracy in
voltage required by JEDEC, and offers an excellent output voltage accuracy and load regulation. Also has a reference
power supply output pin (VREF) for DDR-SDRAM or a memory controller. When EN pin turns to “Low”, VTT output
becomes “Hi-Z” while VREF output is kept unchanged, compatible with “Self Refresh” state of DDR-SDRAM.
Features
1) Incorporates a push-pull power supply for termination (VTT)
2) Incorporates a reference voltage circuit (VREF)
3) Incorporates an enabler
4) Incorporates an under voltage lockout (UVLO)
5) Employs MSOP8 package : 2.9×4.0×0.9(mm) : BD3539FVM
6) Employs VSON008X2030 package : 2.0×3.0×0.6(mm) : BD3539NUX
7) Incorporates a thermal shutdown protector (TSD)
8) Operates with input voltage from 2.7 to 5.5 volts
9) Compatible with Dual Channel (DDR1, DDR2, DDR3)
10) Usable ceramic capacitor at output
Use
Power supply for DDR1- SDRAM (VCC=5V only)
Power supply for DDR2-SDRAM (VCC=3.3V or 5V)
Power supply for DDR3-SDRAM (VCC=3.3V or 5V)
●ABSOLUTE
MAXIMUM RATINGS
Parameter
Input Voltage
Enable Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
Output Current
Power Dissipation1
Power Dissipation2
Power Dissipation3
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Symbol
VCC
VEN
VTT_IN
VDDQ
ITT
Pd1
Pd2
Pd3
Topr
Tstg
Tjmax
Limit
BD3539FVM
7
*1*2
7
*1*2
7
*1*2
7
*1*2
1
387.4
*3
587.4
*4
-
-30½+100
-55½+150
+150
242.0
*4
515.0
*5
877.2
*6
BD3539NUX
Unit
V
V
V
V
A
mW
mW
mW
℃
℃
℃
*1 Should not exceed Pd.
*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.
*3 With Ta≧25℃ (With no heat sink)
θja=322.6℃/W
*4 With Ta≧25℃ when mounting a 70mm×70mm×1.6mm glass-epoxy substrate, with no heat sinkθja=212.8℃/W
*5 With Ta≧25℃ (With no heat sink)
θja=516.5℃/W
*6 With Ta≧25℃ when mounting a 70mm×70mm×1.6mm glass-epoxy substrate 1-layer board,
θja=242.7℃/W
*7 With Ta≧25℃ when mounting a 70mm×70mm×1.6mm glass-epoxy substrate 4-layer board
(copper foil density: 5505mm
2
(copper foil area in each layer) ),
θja=142.5℃/W
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© 2009 ROHM Co., Ltd. All rights reserved.
1/11
2009.10 - Rev.A
BD3539FVM,BD3539NUX
●Operating
Conditions（Ta=25℃）
Parameter
Input Voltage
Termination Input Voltage
VDDQ Reference Voltage
Enable Input Voltage
Symbol
VCC
VTT_IN
VDDQ
VEN
Limit
MIN
2.7
1.0
1.0
-0.3
MAX
5.5
5.5
2.75
5.5
Unit
V
V
V
V
Technical Note
●Electrical
Characteristics
Parameter
Standby Current
Bias Current
[Enable]
(Unless otherwise noted, Ta=25℃, VCC=3.3V, VEN=3V, VDDQ=1.5V, VTT_IN=1.5V）
Limit
Symbol
Unit
Condition
MIN
TYP
MAX
IST
ICC
-
-
0.5
2
1.0
4
mA
mA
VEN=0V
VEN=3V
High Level Enable Input Voltage
Low Level Enable Input Voltage
Enable Pin Input Current
[Termination]
Termination Output Voltage
(DDR3)
Termination Output Voltage
(DDR2)
VENHIGH
VENLOW
IEN
2.3
-0.3
-
-
-
7
5.5
0.8
10
V
V
µA
VEN=3V
ITT=-1.0A to 1.0A
Ta=0℃ to 100℃
VCC = 3.3V, VDDQ = 1.8V
VTT_IN = 1.8V
ITT=-1.0A to 1.0A
Ta=0℃ to 100℃
VCC = 5.0V, VDDQ = 2.5V
VTT_IN = 2.5V
ITT=-1.0A to 1.0A
Ta=0℃ to 100℃
VTT3
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
-15m
+15m
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
-30m
+30m
V
VTT2
V
Termination Output Voltage
(DDR1)
Source current
Sink current
Load Regulation
Upper Side ON Resistance
Lower Side ON Resistance
[VDDQ]
Input Impedance
[VREF]
Output Voltage
[UVLO]
Threshold Voltage
Hysteresis Voltage
VTT1
ITT+
ITT-
⊿VTT
HRON
LRON
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
-30m
+30m
1.0
-
-
-
-
-
-
-
0.35
0.35
-
-1.0
30
0.65
0.65
V
A
A
mV
Ω
Ω
ITT=-1.0A to 1.0A
ZVDDQ
140
200
260
kΩ
IREF=-25mA to 25mA
Ta=0℃ to 100℃
VCC : sweep up
VCC : sweep down
VREF
1/2×VDDQ
1/2×VDDQ
1/2×VDDQ
-15m
+15m
2.30
100
2.45
160
2.60
220
V
VUVLO
⊿VUVLO
V
mV
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© 2009 ROHM Co., Ltd. All rights reserved.
2/11
2009.10 - Rev.A
BD3539FVM,BD3539NUX
●Reference
Data
Technical Note
VTT(50mV/div)
VREF(50mV/div)
VREF(50mV/div)
VTT(50mV/div)
VCC
EN
sink
ITT(1A/div)
ITT(1A/div)
source
10µsec/Div
source
10µsec/Div
VTT
2sec/Div
sink
VDDQ
VTT_IN
Fig.1 DDR3 (-1A→1A)
Fig.2 DDR3 (1A→-1A)
900
Fig.3 Input Sequence1
VCC
VCC
850
800
EN
EN
VTT [mV]
750
700
650
VDDQ
VTT_IN
VDDQ
VTT_IN
VTT
2sec/Div
VTT
2sec/Div
600
-2
-1.5
-1
-0.5
0
ITT[A]
0.5
1
1.5
2
Fig.4 Input Sequence 2
Fig.5 Input Sequence 3
Fig.6 ITT-VTT (DDR3)
751.5
751.0
750.5
VREF [mV]
750.0
749.5
749.0
VDDQ
VTT
VREF
EN
VTT
748.5
-20
-10
0
IREF[mA]
10
20
200µsec/Div
Fig.7 IREF-VREF (DDR3)
Fig.8 EN Soft Start
Fig.9 VDDQ Soft Start
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© 2009 ROHM Co., Ltd. All rights reserved.
3/11
2009.10 - Rev.A
BD3539FVM,BD3539NUX
●Block
Diagram
VCC
C2
VCC
VCC
Reference
Block
UVLO
SOFT
TSD
EN
UVLO
TSD
TSD
VCC EN
UVLO
TSD
EN
UVLO
3
Technical Note
VDDQ
VTT_IN
C3
6
5
VDDQ
VCC
7
VTT_IN
VTT
8
VTT
C4
Thermal
Protection
Enable
EN
EN
VCC
VTTS
4
2
VREF
UVLO
1
½×
VDDQ
C1
GND
●PIN
Configration
○FVM
●PIN
Function
PIN No.
GND 1
EN 2
VTTS 3
VREF 4
8 VTT
7 VTT_IN
6 VCC
5 VDDQ
PIN NAME
GND
EN
VTTS
VREF
VDDQ
VCC
VTT_IN
VTT
PIN FUNCTION
Ground Pin
Enable Input Pin
Detector Pin for Termination Voltage
Reference Voltage Output Pin
Reference Voltage Input Pin
VCC Pin
Termination Input Pin
Termination Output Pin
1
2
3
4
5
6
7
8
○NUX
PIN No.
VTT_IN 1
VTT 2
GND 3
EN 4
8 VCC
7 VDDQ
6 VREF
5 VTTS
PIN NAME
VTT_IN
VTT
GND
EN
VTTS
VREF
VDDQ
VCC
FIN
PIN FUNCTION
Termination Input Pin
Termination Output Pin
Ground Pin
Enable Input Pin
Detector Pin for Termination Voltage
Reference Voltage Output Pin
Reference Voltage Input Pin
VCC Pin
Substrate (Connected to GND)
1
2
3
4
5
6
7
8
Bottom
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© 2009 ROHM Co., Ltd. All rights reserved.
4/11
2009.10 - Rev.A
BD3539FVM,BD3539NUX
Technical Note
●Description
of operations
・VCC
In BD3539FVM/NUX, an independent power input pin is provided for an internal circuit operation of the IC. This is used
to drive the amplifier circuit of the IC, and its maximum current rating is 4mA. The power supply voltage is 2.7 to 5.5 volts.
It is recommended to connect a bypass capacitor of 1μF or so to VCC.
・VDDQ
Reference input pin for the output voltage that may be used to satisfy the JEDEC requirement for DDR3-SDRAM
(VREF=VTT = 1/2VDDQ) by dividing the voltage inside the IC with two 100kΩ voltage-divider resistors.
For BD3539FVM/NUX, care must be taken to an input noise to VDDQ pin because this IC also cuts such noise input into
half and provides it with the voltage output divided in half. Such noise may be reduced with an RC filter consisting of
such resistance and capacitance (220Ω and 2.2μF, for instance) that may not give significant effect to voltage dividing
inside the IC.
・VTT_IN
VTT_IN is a power supply input pin for VTT output. Voltage in the range between 1.0 and 5.5 volts may be supplied to
this VTT_IN terminal, but care must be taken to the current limitation due to on-resistance of the IC and the change in
allowable loss due to input/output voltage difference.
Generally, the following voltages are supplied:
・
DDR3 VTT_IN=1.5V
Higher impedance of the voltage input at VTT_IN may result in oscillation or degradation in ripple rejection, which must be
noted. To VTT_IN terminal, it is recommended to use a 10μF capacitor characterized with less change in capacitance.
But it may depend on the characteristics of the power supply input and the impedance of the pc board wiring, which must
be carefully checked before use.
・VREF
In BD3539FVM/NUX, a reference voltage output pin independent from VTT output is given to provide a reference input for
a memory controller and a DRAM. Even if EN pin turns to “Low” level, VREF output is kept unchanged, compatible with
“Self Refresh” state of DRAM. The maximum current capability of VREF is 10mA, and a suitable capacitor is needed to
stabilize the output voltage. It is recommended to use a combination of a 1.0 to 2.2μF ceramic capacitor characterized
with less change in capacitance. For an application where VREF current is low, a capacitor of lower capacitance may be
used. If VREF current is 1mA or less, it is possible to secure a phase margin with a ceramic capacitor of 1μF more or
less.
・VTTS
An independent pin provided to improve load regulation of VTT output. In case that longer wiring is needed to the load at
VTT output, connecting VTTS from the load side may improve the load regulation.
・VTT
A DDR memory termination output pin. BD3539FVM/NUX has a sink/source current capability of ±1.0A respectively.
The output voltage tracks the voltage divided in half at VDDQ pin. VTT output is turned to OFF when VCC UVLO or
thermal shutdown protector is activated with EN pin level turned to “Low”. Do not fail to connect a capacitor to VTT output
pin for a loop gain phase compensation and a reduction in output voltage variation in the event of sudden change in load.
Insufficient capacitance may cause an oscillation. High ESR (Equivalent Series Resistance) of the capacitor may result
in increase in output voltage variation in the event of sudden change in load. It is recommended to use a 10μF or so
ceramic capacitor, though it depends on ambient temperature and other conditions.
・EN
With an input of 2.3 volts or higher, the level at EN pin turns to “High” to provide VTT output. If the input is lowered to 0.8
volts or less, the level at EN pin turns to “Low” and VTT status turns to Hi-Z. But if VCC and VDDQ are established,
VREF output is maintained.
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© 2009 ROHM Co., Ltd. All rights reserved.
5/11
2009.10 - Rev.A
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