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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE
FUNCTION
ＢＤ９２４４ＡＦＶ
・
・
・
・
・
・
・
・
36V High voltage process
1ch control with Full-Bridge
Lamp current and voltage sense feed back control
Sequencing easily achieved with Soft Start Control
Short circuit protection with Timer Latch
Under Voltage Lock Out and Over Voltage Protection
Mode-selectable the operating or stand-by mode by stand-by pin
BURST mode controlled by PWM and DC input
○Absolute Maximum Ratings（Ｔ½＝２５℃）
Parameter
Supply Voltage
BST PIN
SW PIN
BST-SW voltage difference
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Power Dissipation
*
Symbol
VCC
BST
SW
BST-SW
Topr
Tstg
Tjmax
Pd
Limits
36
40
36
15
-40½+85
-55½+150
+150
1024*
Unit
V
V
V
V
℃
℃
℃
mW
Pd derate at 5.6mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Operating condition
Parameter
Supply voltage
BST voltage
BST-SW voltage difference
oscillation frequency
BCT oscillation frequency
Symbol
VCC
BST
BST-SW
FOUT
fBCT
Limits
9.0½30.0
5.0½37.5
5.0½14.0
30½110
0.05½1.00
Unit
V
V
V
kHz
kHz
REV. A
2/4
○Electric Characteristics（Ta=25℃、VCC=24V、STB=3.0V）
Parameter
（
（WHOLE DEVICE）
）
Operating current
Stand-by current
（
（STAND BY CONTROL）
）
Stand-by voltage H
Stand-by voltage L
（
（VCC UVLO BLOCK）
）
Operating voltage (VCC)
Hesteresis width (VCC UVLO)
Operating voltage (UVLO)
Hesteresis width(UVLO)
Operating voltage (OVP)
Hesteresis width(OVP)
（
（REG BLOCK）
）
REG output voltage
REG source current
（
（OSC BLOCK）
RT Output Voltage
SRT ON Resistor value
（
（SOFT START BLOCK）
）
Soft start time
（
（BOSC BLOCK）
）
BOSC Max voltage
BOSC Min voltage
BOSC frequency
（
（FEED BACK BLOCK）
）
IS threshold voltage
VS threshold voltage
IS source current 1
IS source current 2
VS source current
IS COMP detect voltage
（
（OUTPUT BLOCK）
）
LN output sink resistance
LN output source resistance
HN output sink resistance
HN output source resistance
MAX DUTY
OFF period
Drive output frequency
（
（TIMER
LATCH BLOCK）
VCP
ICP
RFAIL
VIS1
VVS
IIS1
IIS2
IVS
VBCTH
VBCTL
FBCT
TSS
VRT
RSRT
VREG
IREG
VstH
VstL
Icc1
Icc2
Symbol
MIN.
Limits
TYP.
MAX.
Unit
Conditions
－
－
2.2
0
5.0
10
mA
μA
FOUT=60kHz, FB=SW=GND, BST=OPEN
2.0
-0.3
－
－
VCC
1.0
V
V
System
ＯＮ
System
ＯＦＦ
V_VCCUVP
⊿V_VCCUVP
V_UVP
⊿V_UVP
V_OVP
⊿V_OVP
6.17
0.37
1.80
0.15
3.10
0.15
6.50
0.50
1.85
0.20
3.20
0.20
6.83
0.63
1.90
0.25
3.30
0.25
V
V
V
V
V
V
7.35
20
7.50
－
7.65
－
V
mA
VCC>8.5V
1.05
－
1.50
100
1.95
200
V
Ω
2.5
5.0
10.0
ms
FOUT=60kHz
2.16
0.6
291
2.25
0.7
300
2.34
0.8
309
V
V
Hz
fBCT=0.3kHz
fBCT=0.3kHz
BCT=10000pF
1.225
1.215
－
40
－
0.606
1.250
1.250
－
50
－
0.625
1.275
1.285
0.9
60
0.9
0.644
V
V
μA
μA
μA
V
DUTY=2.45V
DUTY=0V IS=1.0V
VISCOMP
RsinkLN
RsourceLN
RsinkHN
RsourceHN
MAX DUTY
TOFF
FOUT
1.5
5
1.5
5
46.0
100
57.9
3
10
3
10
48.5
200
60
6
20
6
20
49.5
400
62.1
Ω
Ω
Ω
Ω
%
ns
kHz
RT=100kΩ
VBST-VSW=7.0V
VBST-VSW=7.0V
FOUT=60kHz
CP timer latch detect voltage
CP timer latch charge current
FAIL ON Resistor value
（
（COMP BLOCK）
）
COMP over voltage detect voltage
Hysteresis width （COMP）
1.9
0.85
－
2.0
1.0
125
2.1
1.15
250
V
μA
Ω
VCOMP
⊿VCOMP
3.88
0.15
4.0
0.20
4.12
0.25
V
V
(
This product is not designed to be radiation-resistant.
)
REV. A
3/4
〇Package Dimensions
〇Block Diagram
VCC
REG
RT
BCT
DUTY
DEVICE MARK
REG
BLOCK
OSC
BLOCK
BOSC
BLOCK
DUTY
BLOCK
STB
STB
BLOCK
SYSTEM ON/OFF
CT
REG
BD9244AFV
BST1
FB
HN1
IS
VS
SW1
F/B
BLOCK
CT
PWM
BLOCK
LOGIC
BLOCK
OUTPUT
BLOCK
LN1
BST2
SS
BLOCK
CT_COUNTER
PROTECT
BLOCK
HN2
SW2
LN2
Lot No.
GND
CT
PGND
VCC
VLO
ブロック
COMP
CP
SRT
VLO
FAIL
SSOP-B24 (UNIT:mm)
○Pin Description
PIN
PIN NAME
No.
FUNCTION
No.
PIN
PIN NAME
FUNCTION
1
PGND
Power Ground for FET drivers
13
FAIL
Error Indication signal output ( Normal : L, Error : OPEN)
2
LN2
NMOS FET driver (Ch. 2)
14
CP
External capacitor between CP and GND for timer latch
3
BST2
Boot-strap input for HN2 output
NMOS FET driver (Ch. 2)
15
FB
Error amplifier output
4
HN2
16
IS
Error amplifier input 2
5
SW2
Lower rail voltage for HN2 output
17
VS
Error amplifier input 1
6
VCC
Power supply input with UVLO Protection
18
COMP
Input of over voltage detector
7
STB
Stand-by switch
External resister from SRT to RT for adjusting the start-up
19
VLO
External Under Voltage Lock Out and Over Voltage Protection
8
SRT
Triangle oscilator
External resistor between RT and GND for adjustment
20
SW1
Lower rail voltage for HN1 output
9
RT
frequency of saw tooth wave
21
HN1
NMOS FET driver (Ch. 1)
10
GND
Ground
External capacitor between BCT and GND for adjusting
22
BST1
Boot-strap input for HN1 output
11
BCT
the BURST triangle oscillator
23
REG
regulator output
12
DUTY
Control Burst-dimming by PWM signal or DC
24
LN1
NMOS FET driver (Ch. 1)
REV. A
4/4
〇NOTE FOR USE
１. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate
margins for steady state and transient characteristics.
２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended
operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges,
however the variation will be small.
３. Mounting failures, such as misdirection or miscounts, may harm the device.
４. A strong electromagnetic field may cause the IC to malfunction.
５. The GND pin should be the location within ±0.3V compared with the PGND pin.
６. If the voltage between VCC and I/O pins or GND and I/O pins is in opposite from the normal potential difference, unusual
current flow into pins may occur which can destroy the IC. To avoid such occurrence it is recommended to place protection
diodes for prevention against backward current flow.
７. BD9244AFV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation of the thermal shutdown circuit is assumed.
８. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened.
Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need
to be considered when using a device beyond its maximum ratings.
９. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
１０. By STB voltage, BD9244AFV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other
state (1.0½2.0V).
１１. The pin connected a connector need to connect to the resistor for electrical surge destruction.
１２．This IC is a monolithic IC which (as shown is Fig.4)has P
+
substrate and between the various pins. A P-N junction is
formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which
parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin
Resistance
(PinA)
(PinB)
Transistor (NPN)
Ｃ
Ｂ
Ｅ
ＧＮＤ
Ｐ
Ｐ
Ｎ
ＧＮＤ
Ｐ
Ｎ
Ｎ
Ｐ
P substrate
Ｐ
Ｎ
Ｎ
Ｐ
Ｎ
Ｎ
P substrate
Parasitic diode
(PinB)
ＧＮＤ
Parasitic diode
(PinA)
Parasitic
Ｂ
Ｃ
Ｅ
ＧＮＤ
Parasitic diode
ＧＮＤ
Other adjacent components
Fig.4. Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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Examples of application circuits, circuit constants and any other information contained herein
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However, should you incur any damage arising from any inaccuracy or misprint of such
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