AT17LV020A-10JC datasheet, PDF

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AT17LV020A-10JC: DescriptionConfiguration Memory, 2MX1, Serial, CMOS, PQCC20, PLASTIC, LCC-20; Categorystorage storage; File Size135KB，13 Pages; ManufacturerAtmel (Microchip)

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AT17LV020A-10JC Overview

Configuration Memory, 2MX1, Serial, CMOS, PQCC20, PLASTIC, LCC-20

AT17LV020A-10JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	QLCC
package instruction	QCCJ, LDCC20,.4SQ
Contacts	20
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	S-PQCC-J20
JESD-609 code	e0
length	8.9662 mm
memory density	2097152 bit
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Humidity sensitivity level	2
Number of functions	1
Number of terminals	20
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX1
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	SERIAL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum standby current	0.0002 A
Maximum slew rate	0.005 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	8.9662 mm

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Features

•

Serial EEPROM Family for Configuring Altera FLEX

Devices

•

Simple Interface to SRAM FPGAs

•

EE Programmable 2-Mbit Serial Memories Designed to Store Configuration Programs

•

for Field Programmable Gate Arrays (FPGAs)

Cascadable Read Back to Support Additional Configurations or Future Higher-density

Arrays

Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available in the Space-efficient Surface-mount PLCC Package

In-System Programmable Via 2-wire Bus

Emulation of Atmel’s AT24CXXX Serial EEPROMs

Available in 3.3V ± 5% LV and 5V ± 5% C Versions

System-friendly READY Pin

Description

The AT17C020A and AT17LV020A (high-density AT17A Series) FPGA Configuration

EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration mem-

ory for programming Altera FLEX

devices. The AT17A Series is packaged in the

popular 20-lead PLCC. The AT17A Series family uses a simple serial-access proce-

dure to configure one or more FPGA devices. The AT17A Series organization supplies

enough memory to configure one or multiple smaller FPGAs. Using a feature of the

AT17A Series, the user can select the polarity of the reset function by programming

internal EEPROM bytes. The AT17A parts generate their own internal clock and can

be used as a system “master” for loading the FPGA devices.

The Atmel devices also support a system-friendly READY pin. The READY pin is used

to simplify system power-up considerations.

The AT17A Series Configurators can be programmed with industry-standard program-

mers, or Atmel’s ATDH2200E Programming Kit.

FPGA

Configuration

EEPROM

Memory

2-megabit

Altera Pinout

AT17C020A

AT17LV020A

Pin Configurations

PLCC

DATA

VCC

nCS

GND

(A2) nCASC

DCLK

SER_EN

READY

Rev. 1270C–05/01

AT17C/LV020A

The READY pin is available as an open-collector indicator of the device’s reset status; it

is driven Low while the device is in its power-on reset cycle and released (tri-stated)

when the cycle is complete.

This document discusses the EPF10K device interface. For more details or information

on other Altera applications, please reference the “AT17A Series Conversions from

Altera FPGA Serial Configuration Memories” application note.

FPGA Device

Configuration

FPGA devices can be configured with an AT17A Series EEPROM as shown in Figure 1.

The AT17A Series device stores configuration data in its EEPROM array and clocks the

data out serially with its internal oscillator. The OE, nCS, and DCLK pins supply the con-

trol signals for the address counter and the output tri-state buffer. The AT17A Series

device sends a serial bitstream of configuration data to its DATA pin, which is connected

to the DATA0 input pin on the FPGA device.

When the configuration data for an FPGA device exceeds the capacity of a single

AT17A Series device, multiple AT17A Series devices can be serially linked together

(Figure 2). When multiple AT17A Series devices are required, the nCASC and nCS pins

provide handshaking between the cascaded EEPROMs.

The position of an AT17A Series device in a chain determines its operation. The first

AT17A Series device in a Configurator chain is powered up or reset with nCS Low and

is configured for the FPGA device’s protocol. This AT17A Series device supplies all

clock pulses to one or more FPGA devices and to any downstream AT17A Series Con-

figurator during configuration. The first AT17A Series Configurator also provides the first

stream of data to the FPGA devices during multi-device configuration. Once the first

AT17A Series device finishes sending configuration data, it drives its nCASC pin Low,

which drives the nCS pin of the second AT17A Series device Low. This activates the

second AT17A Series device to send configuration data to the FPGA device.

The first AT17A Series device clocks all subsequent AT17A Series devices until config-

uration is complete. Once all configuration data is transferred and nCS on the first

AT17A Series device is driven High by CONF_DONE on the FPGA devices, the first

AT17A Series device clocks 16 additional cycles to initialize the FPGA device before

going into zero-power (idle) state. If nCS on the first AT17A Series device is driven High

before all configuration data is transferred – or if the nCS is not driven High after all con-

figuration data is transferred – nSTATUS is driven Low, indicating a configuration error.

The READY pin is available as an open-collector indicator of the device’s reset status; it

is driven Low while the device is in its power-on reset cycle and released (tri-stated)

when the cycle is complete. It can be used to hold the FPGA device in reset while it is

completing its power-on reset but it cannot be used to effectively delay configuration

(i.e., the output is released well before the system V

has stabilized).

AT17C/LV020A

AT17A Series Reset

Polarity

Programming Mode

The AT17A Series Configurator allows the user to program the polarity of the OE pin as

either RESET/OE or RESET/OE. For more details, please reference the “Programming

Specification for Atmel’s FPGA Configuration EEPROMs” application note.

The programming mode is entered by bringing SER_EN Low. In this mode the chip can

be programmed by the 2-wire serial interface. The programming is done at V

supply

only. Programming super voltages are generated inside the chip. See the “Programming

Specification for Atmel’s Configuration EEPROMs” application note for further informa-

tion. The AT17 A-series parts are read/write at 5V nominal. The AT17LV A-series parts

are read/write at 3.3V nominal.

The AT17A Series Configurator enters a low-power standby mode whenever nCS is

asserted High. In this mode, the configuration consumes less than 0.5 mA of current at

5V. The output remains in a high-impedance state regardless of the state of the OE

input.

Standby Mode

Pin Configurations

PLCC

Name

DATA

DCLK

I/O

Description

Three-state data output for configuration. Open-collector bi-directional pin for programming.

Clock output or clock input. Rising edges on DCLK increment the internal address counter and

present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held

High, the nCS input is held Low, and all configuration data has not been transferred to the target

device (otherwise, as the master device, the DCLK pin drives Low).

Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level resets

the address counter. A High logic level (with nCS Low) enables DATA and permits the address

counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and

DCLK drives Low. The logic polarity of this input is programmable and must be programmed active

High (RESET active Low) by the user during programming for Altera applications.

Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the address

counter and enables DATA to drive out. If the AT17A Series is reset with nCS Low, the device

initializes as the first (and master) device in a daisy-chain. If the AT17A Series is reset with nCS

High, the device initializes as a subsequent AT17A Series device in the chain.

Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND pins.

Cascade select output (active Low). This output goes Low when the address counter has reached

its maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device is

usually connected to the nCS input pin of the next device in the chain, which permits DCLK from the

master Configurator to clock data from a subsequent AT17A Series device in the chain.

Device selection input, A2. This is used to enable (or select) the device during programming, (i.e.,

when SER_EN is Low; please refer to the “Programming Specification” application note for more

details).

Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated) when

power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used).

Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low, enables

the 2-wire serial programming mode.

+3.3V/+5V power supply pin

nCS

GND

nCASC

READY

SER_EN

VCC

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