IS61C64AH
8K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is
deselected
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Two Chip Enables (CE1 and CE2) for
simple memory expansion
DESCRIPTION
The
ICSI
IS61C64AH is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using
ICSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns with low power consumption.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C64AH is packaged in the JEDEC standard 28-pin,
300mil SOJ and 330mil SOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
DECODER
256 X 256
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE2
CE1
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR001-B
1
IS61C64AH
PIN CONFIGURATION
28-Pin SOJ and SOP
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A12
CE1
CE2
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.0
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
(1)
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V ± 10%
5V ± 10%
Notes:
1. Industrial supplement specification available upon request.
2
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.5
–2
–2
Max.
—
0.4
V
CC
+ 0.5
0.8
2
2
Unit
V
V
V
V
µA
µA
1
2
3
4
Note:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
1
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE1
≥
V
IH
or
CE2
≥
V
IL
, f = 0
V
CC
= Max.,
CE1
≥
V
CC
– 0.2V,
CE2
≤
0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
-15 ns
Min. Max.
—
—
135
20
-20 ns
Min. Max.
—
—
120
20
-25 ns
Min. Max.
—
—
110
20
Unit
mA
mA
5
6
7
I
SB
2
CMOS Standby
Current (CMOS Inputs)
—
6
—
6
—
6
mA
8
9
10
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
Symbol
C
IN
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
11
12
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Circuit Solution Inc.
SR001-B
3
IS61C64AH
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE1
Access Time
CE2 Access Time
OE
Access Time
-15 ns
Min. Max.
15
—
3
—
—
—
0
—
3
3
—
0
—
—
15
—
15
15
7
—
6
—
—
8
—
15
-20 ns
Min. Max.
20
—
3
—
—
—
0
—
3
3
—
0
—
—
20
—
20
20
7
—
7
—
—
10
—
20
-25 ns
Min. Max.
25
—
3
—
—
—
0
—
3
3
—
0
—
—
25
—
25
25
9
—
9
—
—
12
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
1
t
ACE
2
t
DOE
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
1
(2)
CE1
to Low-Z Output
t
LZCE
2
(2)
CE2 to Low-Z Output
t
HZCE
(2)
CE1
or CE2 to High-Z Output
t
PU
(3)
t
PD
(3)
CE1
or CE2 to Power-Up
CE1
or CE2 to Power-Down
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480
Ω
5V
5V
480
Ω
OUTPUT
30 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1.
Figure 2.
4
Integrated Circuit Solution Inc.
SR001-B
IS61C64AH
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
t
RC
ADDRESS
1
2
t
OHA
DATA VALID
t
AA
t
OHA
D
OUT
PREVIOUS DATA VALID
3
4
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
5
t
OHA
t
AA
OE
6
7
8
t
DOE
CE1
t
HZOE
t
LZOE
CE2
t
LZCE1
t
LZCE2
D
OUT
HIGH-Z
t
ACE1
t
ACE2
DATA VALID
t
HZCE1
t
HZCE2
9
10
11
12
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE1
= V
IL
, CE2 = V
IH
.
3. Address is valid prior to or coincident with
CE1
LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
SR001-B
5
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