HY57V168010D
2 Banks x 1M X 8 Bit Synchronous DRAM
DESCRIPTION
The Hyundai HY57V168010D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory
applications which require large memory density and high bandwidth. HY57V168010D is organized as 2banks of
1,048,576x8.
HY57V168010D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
•
•
•
Single 3.3V
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 44pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM
Internal two banks operation
•
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V168010DTC-8
HY57V168010DTC-10P
HY57V168010DTC-10S
HY57V168010DTC-10
Clock Frequency
125MHz
100MHz
Organization
Interface
Package
2Banks x 1Mbits x 8
100MHz
100MHz
LVTTL
400mil
44pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 1.5/Dec.98
HY57V168010D
PIN CONFIGURATION
VDD
DQ0
VSSQ
DQ1
VDDQ
DQ2
VSSQ
DQ3
VDDQ
NC
NC
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44pin TSOP II
400mil x 725mil
0.8mm pin pitch
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
PIN
CLK
Clock
PIN NAME
DESCRIPTION
The system clock input. All other inputs are referenced to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.
Command input enable or mask except CLK, CKE and DQM
Select either one of banks during both RAS and CAS activity.
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS and WE define the operation.
Refer function truth table for details
DQM control output buffer in read mode and mask input data in write mode
Multiplexed data input / output pin
Power supply for internal circuit and input buffer
Power supply for DQ
No connection
CKE
CS
BA
A0 ~ A10
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
RAS, CAS, WE
DQM
DQ0 ~ DQ7
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 1.5/Dec.98
2
HY57V168010D
FUNCTIONAL BLOCK DIAGRAM
2Mx8 Synchronous DRAM
Self Refresh Counter
Refresh
Interval Timer
Refresh
Counter
1Mx8
Bank 0
Address[0:10]
Sense AMP & I/O gates
Column Decoder
CLK
CKE
BA(A11)
CS
RAS
CAS
WE
DQM
Column Decoder
Sense AMP & I/O gates
Burst Length
Counter
Column Active
Overflow
Column Addr.
Latch & Counter
Precharge
Row Active
Address
Register
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1Mx8
Bank 1
Mode Register
Test Mode
I/O Control
Rev. 1.5/Dec.98
3
HY57V168010D
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature·Time
T
A
T
STG
V
IN
, V
OUT
V
DD
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260·10
Rating
°C
°C
V
V
mA
W
°C
·Sec
Unit
Note : Operation at above absolute maximun rating can adversely affect device reliability.
DC OPERATING CONDITION
(TA=0°C to 70°C)
Parameter
Power Supply Voltage
Input high voltage
Input low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.0
2.0
-0.5
Typ.
3.3
3.0
0
Max
3.6
V
DD
+ 0.3
0.8
Unit
V
V
V
Note
1
1, 2
1, 3
Note :
1.All voltages are referenced to V
SS
= 0V.
2.V
IH
(max) is acceptable 4.6V AC pulse width with
≤
10ns of duration.
3.V
IL
(min) is acceptable -1.5V AC pulse width with
≤
10ns of duration.
AC OPERATING CONDITION
(TA=0°C to 70°C, V
DD
=3.3V
±
0.3V, V
SS
=0V)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
50
Unit
V
V
ns
V
pF
1
Note
Note :
1. Output load to measure access times (tAC, tOH, etc) varies to clock frequency.
A load is equivalent to one TTL gate and one capacitance.
Rev. 1.5/Dec.98
4
HY57V168010D
CAPACITANCE
(TA=25°C, f=1MHz)
Parameter
CLK
Input capacitance
A0 ~ A10, BA
CKE, CS, RAS, CAS, WE,DQM
DQ0 ~ DQ7
Pin
Symbol
C
I1
C
I2
Min
2.5
2.5
Max
4
5
Unit
pF
pF
Data input / output capacitance
C
I/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I
(TA=0°C to 70°C, V
DD
=3.3V
±
0.3V)
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
IL
IO
V
OH
V
OL
Symbol
Min.
-1
-1
2.4
-
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
I
OH
= -4mA
I
OL
=+4mA
Note :
1.V
IN
= 0 to 3.6V, All other pins are not under test = 0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Rev. 1.5/Dec.98
5
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