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1 MSPS, 12-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
AD7262
FEATURES
Dual simultaneous sampling 12-bit, 2-channel ADC
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
1 MSPS for AD7262
500 kSPS for AD7262-5
Analog input impedance: >1 GΩ
Wide input bandwidth
−3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32
Device offset calibration, system gain calibration
On-chip reference: 2.5 V
–40°C to +105°C operation
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
48-lead LFCSP and LQFP packages
FUNCTIONAL BLOCK DIAGRAM
AV
CC
V
REF
A
REF
BUF
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7262
OUTPUT
DRIVERS
V
A
+
V
A
–
PGA
T/H
D
OUT
A
CONTROL
LOGIC
SCLK
CAL
CS
REFSEL
G0
G1
G2
G3
V
DRIVE
OUTPUT
DRIVERS
D
OUT
B
PD0/D
IN
PD1
PD2
V
B
+
V
B
–
PGA
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
BUF
V
REF
B
C
A
_C
B
V
CC
C
A
+
C
A
–
C
B
+
C
B
–
C
A
_C
B
_GND
C
C
_C
D
V
CC
C
C
+
C
C
–
C
D
+
C
D
–
C
C
_C
D
_GND
COMP
COMP
OUTPUT
DRIVERS
OUTPUT
DRIVERS
C
OUT
A
C
OUT
B
GENERAL DESCRIPTION
The AD7262/AD7262-5 are dual, 12-bit, high speed, low power,
successive approximation ADCs that operate from a single 5 V
power supply. The AD7262 features throughput rates of up to
1 MSPS per on-chip ADC. The AD7262-5 features throughput
rates of up to 500 kSPS. Two complete ADC functions allow
simultaneous sampling and conversion of two channels. Each
ADC is preceded by a true differential analog input with a PGA.
There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12,
×16, ×24, ×32, ×48, ×64, ×96, and ×128.
The AD7262/AD7262-5 contain four comparators. Comparator A
and Comparator B are optimized for low power, while Compara-
tor C and Comparator D have fast propagation delays. The
AD7262/AD7262-5 feature a calibration function to remove any
device offset error and programmable gain adjust registers to
allow for input path (for example, sensor) offset and gain
compensation. The AD7262/AD7262-5 have an on-chip 2.5 V
reference that can be disabled if an external reference is preferred.
The AD7262/AD7262-5 are ideally suited for monitoring small
amplitude signals from a variety of sensors. They include all the
functionality needed for monitoring the position feedback
signals from a variety of analog encoders used in motor control
systems.
COMP
OUTPUT
DRIVERS
OUTPUT
DRIVERS
C
OUT
C
C
OUT
D
COMP
AGND
DGND
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC for
the AD7262. The conversion results of both ADCs are
simultaneously available on separate data lines or in succes-
sion on one data line if only one serial port is available.
Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
Internal 2.5 V reference.
3.
4.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
07606-001
AD7262
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 6
Timing Diagram ........................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Circuit Information .................................................................... 15
Comparators................................................................................ 15
Operation..................................................................................... 15
Analog Inputs .............................................................................. 15
V
DRIVE
............................................................................................ 16
Reference ..................................................................................... 17
Typical Connection Diagrams .................................................. 17
Application Details ..................................................................... 20
Modes of Operation ....................................................................... 22
Pin-Driven Mode ....................................................................... 22
Gain Selection ............................................................................. 22
Power-Down Modes .................................................................. 22
Control Register ......................................................................... 23
On-Chip Registers ...................................................................... 24
Serial Interface ................................................................................ 25
Calibration ....................................................................................... 27
Internal Offset Calibration ........................................................ 27
Adjusting the Offset Calibration Registers ................................. 28
System Gain Calibration............................................................ 28
Microprocessor Interfacing ........................................................... 29
AD7262/AD7262-5 to ADSP-BF53x ....................................... 29
Application Hints ........................................................................... 30
Grounding and Layout .............................................................. 30
PCB Design Guidelines for LFCSP .......................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
7/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7262
SPECIFICATIONS
AV
CC
= 4.75 V to 5.25 V, C
A
_C
B
V
CC
= C
C
_C
D
V
CC
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, f
SAMPLE
= 1 MSPS and f
SCLK
= 40 MHz
for AD7262, f
SAMPLE
= 500 kSPS and f
SCLK
= 20 MHz for AD7262-5, V
REF
= 2.5 V internal/external; T
A
= −40°C to +105°C, unless
otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
1
Signal-to-Noise Ratio (SNR)
2
Signal-to-(Noise + Distortion) Ratio
(SINAD)
2
Total Harmonic Distortion (THD)
2
Spurious-Free Dynamic Range (SFDR)
2
Common-Mode Rejection Ratio (CMRR)
3
Min
70
70
Typ
73
72
−85
−97
−76
−77
Max
Unit
dB
dB
dB
dB
dB
Test Conditions/Comments
f
IN
= 100 kHz sine wave
PGA gain setting = 2
For PGA gain setting = 2, ripple
frequency of 50 Hz/60 Hz; see Figure 17
and Figure 18
@ −3 dB; PGA gain setting = 128
@ −3 dB; PGA gain setting = 2
ADC-to-ADC Isolation
3
Bandwidth
3
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Positive Full-Scale Error
2
Positive Full-Scale Error Match
Zero Code Error
2
Zero Code Error Match
Negative Full-Scale Error
2
Negative Full-Scale Error Match
Zero Code Error Drift
ANALOG INPUT
Input Voltage Range, V
IN
+ and V
IN
−
Common-Mode Voltage Range, V
CM
−90
1.2
1.7
12
±1
±0.99
±0.305
dB
MHz
MHz
Bits
LSB
LSB
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
μV/°C
V
V
V
V
V
μA
pF
GΩ
V
V
μA
pF
Ω
ppm/°C
μV rms
±0.5
±0.5
±0.122
±0.018
±0.061
±0.092
±0.012
±0.061
±0.122
±0.018
±0.061
2.5
Guaranteed no missed codes to 12 bits
Pregain calibration
Postgain calibration
Preoffset and pregain calibration
Postoffset and postgain calibration
Pregain calibration
Postgain calibration
±0.244
±0.305
V
CM
±
V
CM
− 100 mV
(V
CC
/2) − 0.4
(V
CC
/2) − 0.4
(V
CC
/2) − 0.6
V
REF
2
×
Gain
V
CM
+ 100 mV
(V
CC
/2) + 0.2
(V
CC
/2) + 0.4
(V
CC
/2) + 0.8
±1
V
CM
= AV
CC
/2; PGA gain setting ≥ 2
V
CM
= 2; PGA gain setting = 1;
see Figure 19
4
V
CM
= AV
CC
/2; PGA gain setting = 2
V
CM
= AV
CC
/2; 3 ≤ PGA gain setting ≤ 32
V
CM
= AV
CC
/2; PGA gain setting ≥ 48
DC Leakage Current
Input Capacitance
3
Input Impedance
3
REFERENCE INPUT/OUTPUT
Reference Output Voltage
5
Reference Input Voltage Range
DC Leakage Current
Input Capacitance
3
V
REF
A, V
REF
B Output Impedance
3
Reference Temperature Coefficient
V
REF
Noise
3
±0.001
5
1
2.495
2.5
2.5
±0.3
20
4
20
20
2.505
±1
2.5 V ± 5 mV max @ 25°C
External reference applied to
Pin V
REF
A/Pin V
REF
B
Rev. 0 | Page 3 of 32
AD7262
Parameter
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating State Leakage Current
Floating State Output Capacitance
3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
COMPARATORS
Input Offset
Comparator A and Comparator B
Comparator C and Comparator D
Offset Voltage Drift
Input Common-Mode Range
3
Input Capacitance
3
Input Impedance
3
I
DD
Normal Mode (Static)
6
Comparator A and Comparator B
Comparator C and Comparator D
Propagation Delay Time
High to Low, t
PHL
Comparator A and Comparator B
Comparator C and Comparator D
Low to High, t
PLH
Comparator A and Comparator B
Comparator C and Comparator D
Delay Matching
Comparator A and Comparator B
Comparator C and Comparator D
±250
±10
ns
ns
Min
0.7 × V
DRIVE
0.8
±1
4
V
DRIVE
− 0.2
0.4
±1
5
Twos complement
19 × t
SCLK
400
1
500
Typ
Max
Unit
V
V
μA
pF
V
V
μA
pF
Test Conditions/Comments
V
IN
= 0 V or V
DRIVE
ns
ns
MSPS
kSPS
AD7262
AD7262-5
±2
±2
0.5
0 to 4
0 to 1.7
4
1
±4
±4
mV
mV
μV/°C
V
V
pF
GΩ
T
A
= 25°C to 105°C only
All comparators
C
A
_C
B
V
CC
= 5 V
C
A
_C
B
V
CC
= 2.7 V
3
6
60
120
8.5
170
μA
μA
μA
μA
25 pF load, C
OUT
x = 0 V, V
CM
= AV
CC
/2,
V
OVERDRIVE
= 200 mV differential
C
A
_C
B
V
CC
= 3.3 V
C
A
_C
B
V
CC
= 5.25 V
C
C
_C
D
V
CC
= 3.3 V
C
C
_C
D
V
CC
= 5.25 V
V
CM
= AV
CC
/2, V
OVERDRIVE
= 200 mV
differential
C
A
_C
B
V
CC
= 2.7 V
C
A
_C
B
V
CC
= 5 V
C
C
_C
D
V
CC
= 2.7 V
C
C
_C
D
V
CC
= 5 V
C
A
_C
B
V
CC
= 2.7 V
C
A
_C
B
V
CC
= 5 V
C
C
_C
D
V
CC
= 2.7 V
C
C
_C
D
V
CC
= 5 V
V
CM
= AV
CC
2, V
OVERDRIVE
= 200 mV
differential
1.4
0.95
0.20
0.13
2
0.93
0.18
0.12
3.5
0.32
μs
μs
μs
μs
μs
μs
μs
μs
4
0.28
Rev. 0 | Page 4 of 32
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