DM54LS373 DM74LS373 DM54LS374 DM74LS374
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
May 1992
DM54LS373 DM74LS373
DM54LS374 DM74LS374
TRI-STATE Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relative-
ly low-impedance loads The high-impedance state and in-
creased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components They are particularly attractive
for implementing buffer registers I O ports bidirectional
bus drivers and working registers
(Continued)
Features
Y
Y
Y
Y
Y
Choice of 8 latches or 8 D-type flip-flops in a single
package
TRI-STATE bus-driving outputs
Full parallel-access for loading
Buffered control inputs
P-N-P inputs reduce D-C loading on data lines
Connection Diagrams
Dual-In-Line Packages
’LS373
Order Number
DM54LS373J
DM54LS373W
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A M20B N20A or
W20A
TL F 6431 – 1
’LS374
Order Number
DM54LS374J
DM54LS374W
DM74LS374WM or
DM74LS374N
See NS Package Number
J20A M20B N20A or
W20A
TL F 6431 – 2
TRI-STATE is a registered trademark of National Semiconductor Corp
C
1995 National Semiconductor Corporation
TL F 6431
RRD-B30M105 Printed in U S A
General Description
(Continued)
The eight latches of the DM54 74LS373 are transparent D-
type latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs When the enable is
taken low the output will be latched at the level of the data
that was set up
The eight flip-flops of the DM54 74LS374 are edge-trig-
gered D-type flip flops On the positive transition of the
clock the Q outputs will be set to the logic states that were
set up at the D inputs
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly
The output control does not affect the internal operation of
the latches or flip-flops That is the old data can be retained
or new data can be entered even while the outputs are off
Function Tables
DM54 74LS373
Output
Control
L
L
L
H
Enable
G
H
H
L
X
D
H
L
X
X
Output
H
L
Q
0
Z
Output
Control
L
L
L
H
DM54 74LS374
Clock
D
H
L
X
X
Output
H
L
Q
0
Z
u
u
L
X
H
e
High Level (Steady State) L
e
Low Level (Steady State) X
e
Don’t Care
e
Transition from low-to-high level Z
e
High Impedance State
Q
0
e
The level of the output before steady-state input conditions were established
u
Logic Diagrams
DM54 74LS373
Transparent Latches
DM54 74LS374
Positive-Edge-Triggered Flip-Flops
TL F 6431– 3
TL F 6431 – 4
2
Absolute Maximum Ratings
(See Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
Input Voltage
Storage Temperature Range
7V
7V
b
65 C to
a
150 C
Note
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Operating Free Air Temperature Range
b
55 C to
a
125 C
DM54LS
DM74LS
0 C to
a
70 C
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
t
W
t
SU
t
H
T
A
Parameter
Min
Supply Voltage
High Level Input Votage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Pulse Width
(Note 2)
Enable High
Enable Low
2)
2)
15
15
5
v
20
v
b
55
DM54LS373
Nom
5
Max
55
07
b
1
DM74LS373
Min
4 75
2
08
b
2 6
Units
Max
5 25
V
V
V
mA
mA
ns
ns
ns
70
C
Nom
5
45
2
12
15
15
5
v
20
v
125
0
24
Data Setup Time (Notes 1
Data Hold Time (Notes 1
Free Air Operating Temperature
Note 1
The symbol (
v
) indicates the falling edge of the clock pulse is used for reference
Note 2
T
A
e
25 C and V
CC
e
5V
’LS373 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
Parameter
Input Clamp Voltage
High Level Output Voltage
Conditions
V
CC
e
Min I
I
e b
18 mA
V
CC
e
Min
I
OH
e
Max
V
IL
e
Max
V
IH
e
Min
V
CC
e
Min
I
OL
e
Max
V
IL
e
Max
V
IH
e
Min
I
OL
e
12 mA
V
CC
e
Min
I
I
I
IH
I
IL
I
OZH
Input Current
Input Voltage
Max
V
CC
e
Max V
I
e
7V
V
CC
e
Max V
I
e
2 7V
V
CC
e
Max V
I
e
0 4V
V
CC
e
Max V
O
e
2 7V
V
IH
e
Min V
IL
e
Max
V
CC
e
Max V
O
e
0 4V
V
IH
e
Min V
IL
e
Max
V
CC
e
Max
(Note 2)
V
CC
e
Max OC
e
4 5V
D
n
Enable
e
GND
3
DM54
DM74
b
20
b
50
Min
Typ
(Note 1)
Max
b
1 5
Units
V
V
DM54
DM74
DM54
DM74
DM74
24
24
34
31
0 25
0 35
04
05
04
01
20
b
0 4
V
OL
Low Level Output Voltage
V
mA
mA
mA
mA
High Level Input Current
Low Level Input Current
Off-State Output Current
with High Level Output
Voltage Applied
Off-State Output Current
with Low Level Output
Voltage Applied
Short Circuit
Output Current
Supply Current
20
I
OZL
b
20
b
100
b
225
mA
mA
mA
I
OS
I
CC
24
40
‘LS373 Switching Characteristics
at V
CC
e
5V and T
A
e
25 C
(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)
Data
to
Q
Data
to
Q
Enable
to
Q
Enable
to
Q
Output
Control
to Any Q
Output
Control
to Any Q
Output
Control
to Any Q
Output
Control
to Any Q
R
L
e
667X
C
L
e
45 pF
Min
Max
18
C
L
e
150 pF
Min
Max
26
ns
Units
Symbol
Parameter
t
PLH
Propagation Delay
Time Low to High
Level Output
Propagation Delay
Time High to Low
Level Output
Propagation Delay
Time Low to High
Level Output
Propagation Delay
Time High to Low
Level Output
Output Enable
Time to High
Level Output
Output Enable
Time to Low
Level Output
Output Disable
Time from High
Level Output (Note 3)
Output Disable
Time from Low
Level Output (Note 3)
t
PHL
18
27
ns
t
PLH
30
38
ns
t
PHL
30
36
ns
t
PZH
28
36
ns
t
PZL
36
50
ns
t
PHZ
20
ns
t
PLZ
25
ns
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
C
L
e
5 pF
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
t
W
t
SU
t
H
T
A
Parameter
Min
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Pulse Width
(Note 4)
Data Setup Time (Notes 1
Data Hold Time (Notes 1
Clock High
Clock Low
4)
4)
15
15
20
u
1
u
b
55
DM54LS374
Nom
5
Max
55
Min
4 75
2
07
b
1
DM74LS374
Nom
5
Max
5 25
Units
V
V
08
b
2 6
45
2
V
mA
mA
ns
ns
ns
12
15
15
20
u
1
u
125
0
24
Free Air Operating Temperature
70
C
Note 1
The symbol ( ) indicates the rising edge of the clock pulse is used for reference
Note 4
T
A
e
25 C and V
CC
e
5V
u
4
’LS374 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
Parameter
Input Clamp Voltage
High Level Output Voltage
Conditions
V
CC
e
Min I
I
e b
18 mA
V
CC
e
Min
I
OH
e
Max
V
IL
e
Max
V
IH
e
Min
V
CC
e
Min
I
OL
e
Max
V
IL
e
Max
V
IH
e
Min
I
OL
e
12 mA
V
CC
e
Min
I
I
I
IH
I
IL
I
OZH
Input Current
Input Voltage
Max
V
CC
e
Max V
I
e
7V
V
CC
e
Max V
I
e
2 7V
V
CC
e
Max V
I
e
0 4V
V
CC
e
Max V
O
e
2 7V
V
IH
e
Min V
IL
e
Max
DM54
DM74
24
24
34
31
V
Min
Typ
(Note 1)
Max
b
1 5
Units
V
V
OL
Low Level Output Voltage
DM54
DM74
0 25
0 35
04
05
V
DM74
0 25
04
01
20
b
0 4
mA
mA
mA
High Level Input Current
Low Level Input Current
Off-State Output
Current with High
Level Output
Voltage Applied
Off-State Output
Current with Low
Level Output
Voltage Applied
Short Circuit
Output Current
Supply Current
20
mA
I
OZL
V
CC
e
Max V
O
e
0 4V
V
IH
e
Min V
IL
e
Max
b
20
mA
I
OS
I
CC
V
CC
e
Max
(Note 2)
V
CC
e
Max D
n
e
GND OC
e
4 5V
DM54
DM74
b
50
b
50
b
225
b
225
mA
mA
27
45
’LS374 Switching Characteristics
at V
CC
e
5V and T
A
e
25 C
(See Section 1 for Test Waveforms and Output Load)
R
L
e
667X
Symbol
Parameter
C
L
e
45 pF
Min
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock Frequency
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Output Enable Time
to High Level Output
Output Enable Time
to Low Level Output
Output Disable Time
from High Level Output (Note 3)
Output Disable Time
from Low Level Output (Note 3)
35
28
28
28
28
20
25
Max
C
L
e
150 pF
Min
20
32
38
44
44
Max
MHz
ns
ns
ns
ns
ns
ns
Units
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
C
L
e
5 pF
5
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