IDT74FCT163374A/C
3.3V CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
REGISTER (3-STATE)
IDT74FCT163374A/C
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range, or V
CC
= 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4μ W typ. static)
μ
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP and TSSOP packages
FEATURES:
DESCRIPTION:
The FCT163374 16-bit edge-triggered D-type register is built using
advanced dual metal CMOS technology. These high-speed, low-power
registers are ideal for use as buffer registers for data synchronization and
storage. The Output Enable (xOE) and clock (xCLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins facilitates ease of
layout. All inputs are designed with hysteresis for improved noise margin.
The inputs of FCT163374 can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as translators in a mixed 3.3V/
5V supply system.
FUNCTIONAL BLOCK DIAGRAM
1
1
OE
1
CLK
1
D
1
48
24
2
OE
25
2
CLK
47
D
2
1
O
1
2
D
1
36
D
13
2
O
1
C
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2018
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2018
DSC-2775/13
IDT74FCT163374A/C
3.3V CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
O
1
1
O
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +4.6
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
CLK
1
D
1
1
D
2
V
TERM
(3)
V
TERM
(4)
T
STG
I
OUT
GND
1
O
3
1
O
4
GND
1
D
3
1
D
4
V
CC
1
O
5
1
O
6
V
CC
1
D
5
1
D
6
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
GND
1
O
7
1
O
8
2
O
1
2
O
2
GND
1
D
7
1
D
8
2
D
1
2
D
2
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
GND
2
O
3
2
O
4
GND
2
D
3
2
D
4
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
xDx
xCLK
xOx
xOE
Description
Data Inputs
Clock Inputs
3-State Outputs
3-State Output Enable Input (Active LOW)
V
CC
2
O
5
2
O
6
V
CC
2
D
5
2
D
6
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
CLK
FUNCTION TABLE
(1)
Function
Hi-Z
xDx
X
X
L
H
L
H
Inputs
xCLK
L
H
↑
↑
↑
↑
xOE
H
H
L
L
H
H
Outputs
xOx
Z
Z
L
H
Z
Z
TOP VIEW
Package Type
TSSOP
SSOP
Package Code
PAG48
PVG48
Order Code
PAG
PVG
Load Register
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH transition
2
IDT74FCT163374A/C
3.3V CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 2.7V to 3.6V
Symbol
V
IH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
V
IL
I
IH
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Short Circuit Current
(4)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Max., V
O
= GND
(3)
—
–60
—
—
–135
150
0.1
–240
—
10
mA
mV
µA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
I
OL
= 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
0.55
0.5
V
I
OH
= –0.1mA
I
OH
= –3mA
I
OH
= –8mA
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= V
CC
V
I
= GND
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Min.
2
2
–0.5
—
—
—
—
—
—
—
–36
50
V
CC
-0.2
2.4
2.4
(5)
Typ.
(2)
—
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3
3
Max.
5.5
V
CC
+0.5
0.8
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
V
V
mA
mA
µA
µA
V
Unit
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
–0.6V at rated current.
3
IDT74FCT163374A/C
3.3V CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= V
CC
–0.6V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz
50% Duty Cycle
xOE = GND
f
i
= 5MHz
One Bit Toggling
V
CC
= Max., Outputs Open
f
CP
= 10MHz
50% Duty Cycle
xOE = GND
f
i
= 2.5MHz
Sixteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
2
50
Max.
30
75
Unit
µA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
—
0.5
0.8
mA
—
—
—
0.5
2.5
2.5
0.8
3.8
(5)
4
(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+ DI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at fi
4
IDT74FCT163374A/C
3.3V CMOS 16-BIT REGISTER (3-STATE)
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xCLK to xOx
Output Enable Time
Output Disable Time
Set-up Time HIGH or LOW, xDx to xCLK
Hold Time HIGH or LOW, xDx to xCLK
xCLK Pulse Width HIGH
Output Skew
(4)
Condition
(2)
C
L
= 50pF
R
L
= 500Ω
FCT163374A
Min.
(3)
Max.
2
6.5
1.5
1.5
2
1.5
5
—
6.5
5.5
—
—
—
0.5
FCT163374C
Min.
(3)
Max.
2
5.2
1.5
1.5
2
1.5
5
—
5.5
5
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Propagation Delays and Enable/Disable times are with V
CC
= 3.3V ±0.3V, Normal Range. For V
CC
= 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable
times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
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