IDT7034S20PF8 datasheet, PDF - EEWORLD Datasheet

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IDT7034S20PF8: DescriptionDual-Port SRAM, 4KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100; Categorystorage storage; File Size198KB，19 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT7034S20PF8 Overview

Dual-Port SRAM, 4KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT7034S20PF8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	20 ns
I/O type	COMMON
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	73728 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	100
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.015 A
Minimum standby current	4.5 V
Maximum slew rate	0.29 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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HIGH-SPEED

4K x 18 DUAL-PORT

STATIC RAM

Features:

IDT7034S/L

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

Commercial: 15/20ns (max.)

Low-power operation

IDT7034S

Active: 850mW (typ.)

Standby: 5mW (typ.)

IDT7034L

Active: 850mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT7034 easily expands data bus width to 36 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for

BUSY

output flag on Master

M/S = L for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (40°C to +85°C) is available

for selected speeds

Functional Block Diagram

I/O

-I/O

17L

I/O

-I/O

BUSY

(1,2)

I/O

Control

I/O

Control

I/O

-I/O

17R

I/O

-I/O

BUSY

(1,2)

11L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

11R

SEM

(2)

INT

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEM

(2)

INT

4089 drw 01

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

SEPTEMBER 1999

DSC 4089/6

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