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IDT707278L25PFI

Description
Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Categorystorage    storage   
File Size133KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT707278L25PFI Overview

Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT707278L25PFI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts100
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time25 ns
I/O typeCOMMON
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply5 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.01 A
Minimum standby current4.5 V
Maximum slew rate0.31 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
HIGH-SPEED
32K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
x
IDT707278S/L
Features
32K x 16 Bank-Switchable Dual-Ported SRAM Architecture
– Four independent 8K x 16 banks
– 512 Kilobit of memory on chip
Fast asynchronous address-to-data access time: 15ns
User-controlled input pins included for bank selects
Independent port controls with asynchronous address &
data busses
Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
x
x
x
x
x
x
x
x
Interrupt flags with programmable masking
Dual Chip Enables allow for depth expansion without
external logic
UB
and
LB
are available for x8 or x16 bus matching
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
x
Functional Block Diagram
MUX
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
8Kx16
MEMORY
ARRAY
(BANK 0)
MUX
I/O
8L-15L
I/O
0L-7L
I/O
CONTROL
MUX
8Kx16
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
8R-15R
I/O
0R-7R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
CONTROL
LOGIC
A
12L
A
0L(1)
ADDRESS
DECODE
ADDRESS
DECODE
A
12R
A
0R(1)
BA
1L
BA
0L
BANK
DECODE
MUX
8Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BANK
DECODE
BA
1R
BA
0R
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
A
5L(1)
A
0L(1)
LB
L
/UB
L
OE
L
R/W
L
CE
L
MAILBOX
INTERRUPT
LOGIC
A
5R(1)
A
0R(1)
LB
R
/UB
R
OE
R
R/W
R
CE
R
MBSEL
L
INT
L
MBSEL
R
INT
R
3739 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL
= V
IH
, the pins serve as memory address inputs. When
MBSEL
= V
IL
, the pins
serve as mailbox address inputs.
2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for
more details.
MAY 2000
1
©2000 Integrated Device Technology, Inc.
DSC 3739/6

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