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IDT70824L25PFI8

Description
Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80
Categorystorage    storage   
File Size193KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70824L25PFI8 Overview

Standard SRAM, 4KX16, 25ns, CMOS, PQFP80, TQFP-80

IDT70824L25PFI8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionTQFP-80
Contacts80
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time25 ns
JESD-30 codeS-PQFP-G80
JESD-609 codee0
length14 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of terminals80
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4KX16
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
HIGH SPEED 64K (4K X 16 BIT)
IDT70824S/L
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM
)
Features
High-speed access
– Military: 35/45ns (max.)
– Commercial: 20/25/35/45ns (max.)
Low-power operation
– IDT70824S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70824L
Active: 775mW (typ.)
Standby: 1mW (typ.)
4K x 16 Sequential Access Random Access Memory (SARAM
)
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
High speed operation
– 20ns t
AA
for random access port
– 20ns t
CD
for sequential port
– 25ns clock cycle time
Architecture based on Dual-Port RAM cells
Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random
Access Memory (SARAM). The SARAM offers a single-chip solution to
buffer data sequentially on one port, and be accessed randomly (asyn-
chronously) through the other port. The device has a Dual-Port RAM
based architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
A
0-11
CE
OE
R/W
LB
LSB
MSB
UB
CMD
I/O
0-15
12
Random
Access
Port
Controls
Sequential
Access
Port
Controls
4K X 16
Memory
Array
16
12
12
12
12
12
RST
SCLK
CNTEN
SOE
SSTRT
1
SSTRT
2
SCE
SR/W
SLD
SI/O
0-15
,
Data
L
Addr
L
Data
R
Addr
R
16
Reg.
12
16
RST
Pointer/
Counter
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
12
EOB
1
COMPARATOR
EOB
2
3099 drw 01
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC-3099/6
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