IDT70825S/L
HIGH SPEED 128K (8K X 16 BIT)
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
◆
Features
High-speed access
– Commercial: 20/25/35/45ns (max.)
Low-power operation
– IDT70825S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70825L
Active: 775mW (typ.)
Standby: 1mW (typ.)
8K x 16 Sequential Access Random Access Memory
(SARAM
™
)
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
High speed operation
– 20ns t
AA
for random access port
– 20ns t
CD
for sequential port
– 25ns clock cycle time
Architecture based on Dual-Port RAM cells
◆
◆
◆
◆
◆
◆
◆
◆
◆
Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Description
The IDT70825 is a high-speed 8K x 16-Bit Sequential Access
Random Access Memory (SARAM). The SARAM offers a single-chip
solution to buffer data sequentially on one port, and be accessed
randomly (asynchronously) through the other port. The device has a
Dual-Port RAM based architecture with a standard SRAM interface for the
random (asynchronous) access port, and a clocked interface with counter
◆
◆
Functional Block Diagram
A
0-12
CE
OE
R/W
LB
LSB
MSB
UB
CMD
I/O
0-15
13
Random
Access
Port
Controls
Sequential
Access
Port
Controls
8K X 16
Memory
Array
16
13
RST
SCLK
CNTEN
SOE
SSTRT
1
SSTRT
2
SCE
SR/W
SLD
SI/O
0-15
,
Data
L
Addr
L
Data
R
Addr
R
16
Reg.
13
16
13
13
13
13
RST
Pointer/
Counter
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
13
EOB
1
COMPARATOR
EOB
2
3016 drw 01
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC-3016/10
6.07
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
sequencing for the sequential (synchronous) access port.
Fabricated using CMOS high-performance technology, this memory
device typically operates on less than 775mW of power at maximum
high-speed clock-to-data and Random Access. An automatic power
down feature, controlled by
CE,
permits the on-chip circuitry of each port
to enter a very low standby power mode.
The IDT70825 is packaged in a 80-pin Thin Quad Flatpack (TQFP)
or 84-pin Pin Grid Array (PGA).
INDEX
SI/O
1
SI/O
0
GND
N/C
SCE
SR/W
RST
SLD
SSTRT
2
SSTRT
1
GND
GND
CNTEN
SOE
SCLK
GND
EOB
2
EOB
1
V
CC
I/O
0
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
2
58
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
SI/O
2
SI/O
3
V
CC
SI/O
4
SI/O
5
SI/O
6
SI/O
7
GND
SI/O
8
SI/O
9
SI/O
10
SI/O
11
V
CC
SI/O
12
SI/O
13
SI/O
14
SI/O
15
GND
N/C
A
12
IDT70825PF
PN80-1
(4)
80-PinTQFP
Top View
(5)
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
V
CC
V
CC
A
1
A
0
CMD
CE
LB
UB
R/W
OE
3016 drw 02
,
Pin Configurations
(1,2,3)
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
63
61
I/O
1
GND
I/O
2
I/O
3
V
CC
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
V
CC
I/O
12
I/O
13
I/O
14
I/O
15
GND
60
58
55
54
51
48
46
45
42
I/O
1
66
V
CC
64
EOB
1
GND
CNTEN
GND
SSTRT2
SR/W NC
62
59
56
49
50
47
44
GND
43
NC
40
11
10
09
08
07
06
05
04
03
02
01
,
I/O
2
67
NC
65
I/O
0
EOB
2
SOE
57
RST SLD
53
52
SCE
SI/O
0
SI/O
1
SI/O
3
41
39
I/O
3
GND
69
68
SCLK GND
SSTRT1
SI/O
2
V
CC
38
37
I/O
4
72
V
CC
71
73
33
SI/O
4
SI/O
5
35
34
I/O
7
75
I/O
6
GND
70
74
IDT70825G
G84-3
(4)
84-Pin PGA
Top View
(5)
SI/O
8
SI/O
7
GND
32
31
36
I/O
9
76
I/O
5
77
I/O
8
78
SI/O
9
SI/O
10
SI/O
6
28
29
30
I/O
10
I/O
11
V
CC
79
80
SI/O
12
V
CC
SI/O
11
26
27
I/O
12
I/O
13
81
83
7
11
12
SI/O
14
SI/O
13
23
25
I/O
14
82
NC
1
2
5
CMD
V
CC
8
10
A
2
14
17
20
NC SI/O
15
22
24
I/O
15
GND
84
3
4
OE
6
LB
9
A
0
A
1
E
V
CC
15
A
4
13
A
7
16
A
10
18
A
12
19
GND
21
NC
A
INDEX
R/W
B
UB
C
CE
D
A
5
F
A
3
G
A
6
H
A
8
J
A
9
K
A
11
L
3016 drw 03
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN-80-1 package body is approximately 14mm x 14mm x 1.4mm.
G84-3 package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Pin Descriptions: Random Access Port
(1)
SYMBOL
A
0-
A
12
I/O
0
-I/O
15
CE
NAME
Address Lines
Inputs/Outputs
Chip Enable
I/O
I
I
I
DESCRIPTIONS
Address inputs to access the 8192-word (16-Bit) memory array.
Random access data inputs/outputs for 16-Bit wide data.
When
CE
is LOW, the random access port is enabled. When
CE
is HIGH, the random access port is disabled
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during
CE
=
V
IH
, unless it is altered by the sequential port.
CE
and
CMD
may not be LOW at the same time.
When
CMD
is LOW, address lines A
0
-A
2
, R/W, and inputs/outputs I/O
0
-I/O
12
, are used to access the control
register, the flag register, and the start and end of buffer registers.
CMD
and
CE
may not b e LOW at the same
time.
If
CE
is LOW and
CMD
is HIGH, data is written into the array when R/W is LOW and read o ut of the array when
R/W is HIGH. If
CE
is HIGH and
CMD
is LOW, R/W is used to access the buffer command registers.
CE
and
CMD
may not be LOW at the same time.
When
OE
is LOW and R/W is HIGH, I/O
0
-I/O
15
outputs are enabled. When
OE
is HIGH, the I/O outputs are in
the High-impedance state.
When
LB
is LOW, I/O
0
-I/O
7
are accessible for read and write operations. When
LB
is HIGH I/O
0
-I/O
7
are tri-
stated and blocked during read and write operations.
UB
controls access for I/O
8
-I/O
15
in the same manner and
is asynchronous from
LB.
Seven +5V powe r supply pins. All V
CC
pins must be connected to the same +5V V
CC
supply.
Ten ground pins. All ground pins must be connected to the same ground supply.
3016 tbl 01
CMD
Control Register
Enable
Read/Write Enable
I
R/W
I
OE
LB, UB
Output Enable
Lower Byte, Upper
Byte Enables
Power Supply
Ground
I
I
V
CC
GND
I
I
Pin Descriptions: Sequential Access Port
(1)
SYMBOL
SI/O
0-15
SCLK
SCE
NAME
Inputs/Outputs
Clock
Chip Enable
I/O
I
I
I
DESCRIPTIONS
Sequential data inputs/outputs for 16-bit wide data.
SI/O
0
-SI/O
15
,
SCE,
SR/W, and
SLD
are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential
access port address pointer increments by 1 on each LOW-to-HIGH transition of SCLK when
CNTEN
is LOW.
When
SCE
is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When
SCE
is HIGH, the sequential access port is disabled into powere d-down mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained, unless altered by the random
access port.
When
CNTEN
is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
independent of
CE.
When SR/W and
SCE
are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/
W
is
HIGH, and
SCE
and
SOE
are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination
of a write cycle is done on the LOW-to-HIGH transition of SCLK if SR/W or
SCE
is HIGH.
When
SLD
is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When
SLD
is LOW, data on the inputs SI/O
0
-SI/O
12
is loaded into a data-in registe r on the LOW-to-HIGH transition of
SCLK. On the cycle following
SLD,
the address pointer changes to the addre ss location contained in the data-
in register.
SSTRT
1
and
SSTRT
2
may not be LOW while
SLD
is LOW or during the cycle following
SLD.
When
SSTRT
1
or
SSTRT
2
is LOW, the start of address register #1 or #2 is lo aded into the address pointer on
the LOW-to-HIGH transition of SCLK. The start address are stored in internal registers.
SSTRT
1
and
SSTRT
2
may not be LOW while
SLD
is LOW or during the cycle following
SLD.
EOB
1
or
EOB
2
is output LOW when the address pointer is incremented to match the address stored in the end
of the buffer registers. The flags can be cleared by either asserting
RST
LOW or by writing zero into Bit 0
and/or Bit 1 of the control register at address 101.
EOB
1
and
EOB
2
are dependent on separate internal
registers, and therefore separate match addresses.
SOE
controls the data outputs and is independent of SCLK. When
SOE
is LOW, output buffers and the
sequentially addressed d ata is output. When
SOE
is HIGH, the SI/O output bus is in the High-impedance state.
SOE
is asynchronous to SCLK.
When
RST
is LOW, all internal registers are set to their default state, the address pointer is set to zero and the
EOB
1
and
EOB
2
flags are set HIGH. Rst is asynchronous to SCLK.
3016 tbl 02
CNTEN
SR/W
Control Enable
Read/Write Enable
I
I
SLD
Address Pointer
Load Control
I
SSTRT
1
,
SSTRT
2
Load Start of
Address Register
I
EOB
1
,
EOB
2
End of Buffer Flag
I
SOE
Output Enable
I
RST
Reset
I
NOTE:
1. "I/O" is bidirectional input and output. "I" is input and "O" is output.
6.42
3
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Recommended Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
3016 tbl 04a
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
Industrial
o
mA
3016 tbl 03a
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
>
Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
3016 tbl 05
Capacitance
Symbol
C
IN
C
OUT
(T
A
= +25°C, f = 1.0mhz, TQFP only)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3016 tbl 06
V
IL
____
NOTES:
1. V
IL
> –1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization, but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VCC = 5.0V ± 10%)
70825S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
70825L
Max.
5
5
0.4
___
Min.
___
___
Max.
1
1
0.4
___
Unit
µA
µA
V
V
3016 tbl 07
___
___
2.4
2.4
4
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,2,8)
(V
CC
= 5.0V ± 10%)
70825X20
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Full Standby Current
(One Port -
CMOS Level Inputs)
Test Condition
CE
= V
IL
,
Outputs Disabled
SCE
= V
IL
(5)
f = f
MAX
(3)
SCE
and
CE
> V
IH
(7)
CMD
= V
IH
f = f
MAX
(3)
CE
or
SCE
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
Both Ports
CE
and
SCE
> V
CC
- 0.2V
(6,7)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
One Port
CE
or
SCE
> V
CC
- 0.2V
(6)
Outputs Disabled (Active Port)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
f = f
MAX
(3)
Version
COM'L
S
L
Typ.
180
180
Max.
380
330
70825X25
Com'l Only
Typ.
170
170
Max.
360
310
70825X35
Com'l Only
Typ.
160
160
Max.
340
290
70825X45
Com'l Only
Typ.
155
155
Max.
340
290
Unit
mA
I
SB1
COM'L
S
L
S
L
25
25
115
115
70
50
260
230
25
25
105
105
70
50
250
220
20
20
95
95
70
50
240
210
16
16
90
90
70
50
240
210
mA
I
SB2
COM'L
mA
I
SB3
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
I
SB4
COM'L
S
L
110
110
240
200
100
100
230
190
90
90
220
180
85
85
220
180
mA
3016 tbl 08a
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25°C; guaranteed by device characterization but not production tested.
3. At f = f
MAX
, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/t
RC.
4. f = 0 means no address or control lines change.
5.
SCE
may transition, but is LOW (SCE=V
IL
) when clocked in by SCLK.
6.
SCE
may be - 0.2V, after it is clocked in, since SCLK=V
IH
must be clocked in prior to powerdown.
7. If one port is enabled (either
CE
or
SCE
= LOW) then the other port is disabled (SCE or
CE
= HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and
TTL HIGH = V
IH
and LOW = V
IL
.
8. Industrial temperature: for other speeds, packages and powers contact your sales office.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only)
(V
LC
< 0.2V, V
HC
> V
CC
- 0.2V)
Symbol
V
DR
I
CCDR
Parameter
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V
CE
> V
HC
V
IN
= V
HC
or = V
LC
t
CDR
(3)
t
R
(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
IND.
COM'L.
Test Condition
Min.
2.0
___
Typ.
(1)
___
Max.
___
Unit
V
µA
100
100
___
4000
1500
___
___
SCE
= V
HC
(4)
when SCLK =
↑
CMD
= V
HC
___
V
V
3016 tbl 09a
t
RC
(2)
___
___
NOTES :
1. T
A
= +25°C, V
CC
= 2V; guaranteed by device characterization but not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention,
SCE
= V
IH
must be clocked in.
6.42
5
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