IDT70T3399S133DD datasheet, PDF

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IDT70T3399S133DD: DescriptionDual-Port SRAM, 128KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144; Categorystorage storage; File Size300KB，27 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70T3399S133DD Overview

Dual-Port SRAM, 128KX18, 15ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144

IDT70T3399S133DD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
Contacts	144
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	15 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
memory density	2359296 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	4
Number of functions	1
Number of ports	2
Number of terminals	144
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.015 A
Minimum standby current	2.4 V
Maximum slew rate	0.37 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	20 mm

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HIGH-SPEED 2.5V

512/256/128K X 18

IDT70T3339/19/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– Data input, address, byte enable and control registers

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data,

and address inputs @ 200MHz

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine

pitch Ball Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

0 1

L L

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

FT/PIPE

0/1

0a 1a 0b

0/1

FT/PIPE

512/256/128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

18L

(1)

REPEAT

ADS

CNTEN

18R (1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1R

JTAG

TDO

COL

INT

(2)

COL

INT

CONTROL

LOGIC

(2)

5652 drw 01

NOTES:

1. Address A

is a NC for the IDT70T3319. Also, Addresses A

and A

are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

APRIL 2010

DSC-5652/7

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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