IDT70T3509MS133BPGI datasheet, PDF

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IDT70T3509MS133BPGI: DescriptionDual-Port SRAM, 1MX36, 15ns, CMOS, PBGA256, GREEN, BGA-256; Categorystorage storage; File Size256KB，23 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70T3509MS133BPGI Overview

Dual-Port SRAM, 1MX36, 15ns, CMOS, PBGA256, GREEN, BGA-256

IDT70T3509MS133BPGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	LBGA, BGA256,16X16,40
Contacts	256
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	15 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B256
JESD-609 code	e1
length	17 mm
memory density	37748736 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	256
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.08 A
Minimum standby current	2.4 V
Maximum slew rate	1.37 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm

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HIGH-SPEED 2.5V

1024K x 36

IDT70T3509M

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 4.2ns (133MHz)(max.)

– Industrial: 4.2ns (133MHz)(max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Interrupt Flags

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 133MHz

– Fast 4.2ns clock to data out

◆

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Includes JTAG functionality

Available in a 256-pin Ball Grid Array (BGA)

Common BGA footprint provides design flexibility over

seven density generations (512K to 36M-bit)

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

1/0

FT/PIPE

R/W

(2)

1/0

B B B

WW W

2 3 3

L L R

B B

1 0

R R

1/0

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c 1b 0b 1a 0a

0a 1a 0b 1b 0c 1c 0d 1d

0/1

FT/PIPE

0/1

a b cd

dcba

1024K x 36

MEMORY

ARRAY

I/O

- I/O

35L

Din_L

Din_R

I/O

- I/O

35R

CLK

19L

REPEAT

ADS

CNTEN

19R

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

LOGIC

0 R

CE1R

JTAG

TDO

INT

(1)

INT

CONTROL

LOGIC

(1)

5682 drw 01

NOTE:

1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

2. See Truth Table I for Functionality.

AUGUST 2007

DSC 5682/7

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