IDT70T659S15BFG8 datasheet, PDF

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IDT70T659S15BFG8: DescriptionDual-Port SRAM, 128KX36, 15ns, CMOS, PBGA208, FBGA-208; Categorystorage storage; File Size345KB，27 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT70T659S15BFG8 Overview

Dual-Port SRAM, 128KX36, 15ns, CMOS, PBGA208, FBGA-208

IDT70T659S15BFG8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	FBGA-208
Contacts	208
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	15 ns
I/O type	COMMON
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	208
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA208,17X17,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum standby current	0.01 A
Minimum standby current	2.4 V
Maximum slew rate	0.305 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm

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Features

◆

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

PRELIMINARY

IDT70T651/9S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

◆

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

BBBB

EEEE

3210

R RRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

17L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

17R(1)

R/W

BUSY

L (2,3)

SEM

INT

L(3)

(4)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

TDI

TD O

JTAG

TC K

TMS

TRST

M/S

BUSY

R(2,3)

SEM

INT

R(3)

(4)

NOTES:

1. Address A

17x

is a NC for IDT70T659.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

4869 drw 01

NOVEMBER 2003

DSC-5632/3

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