EPM5128JC68-1 datasheet, PDF - EEWORLD Datasheet

EPM5128JC68-1: DescriptionUV PLD, 40ns, 128-Cell, CMOS, CQCC68, WINDOWED, CERAMIC, LCC-68; CategoryProgrammable logic devices Programmable logic; File Size732KB，35 Pages; ManufacturerAltera (Intel)

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EPM5128JC68-1 Overview

UV PLD, 40ns, 128-Cell, CMOS, CQCC68, WINDOWED, CERAMIC, LCC-68

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	LCC
package instruction	WQCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	unknown
Other features	128 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS
maximum clock frequency	50 MHz
In-system programmable	NO
JESD-30 code	S-CQCC-J68
JESD-609 code	e0
JTAG BST	NO
length	24.13 mm
Dedicated input times	7
Number of I/O lines	52
Number of macro cells	128
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
organize	7 DEDICATED INPUTS, 52 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	WQCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER, WINDOW
Peak Reflow Temperature (Celsius)	220
power supply	5 V
Programmable logic type	UV PLD
propagation delay	40 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.13 mm

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