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HY62QF16201ALLM-70

Description
Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, MICRO, CSP, BGA-48
Categorystorage    storage   
File Size205KB,13 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HY62QF16201ALLM-70 Overview

Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, MICRO, CSP, BGA-48

HY62QF16201ALLM-70 Parametric

Parameter NameAttribute value
MakerSK Hynix
Parts packaging codeBGA
package instructionFBGA,
Contacts48
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time70 ns
JESD-30 codeR-PBGA-B48
JESD-609 codee1
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals48
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX16
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)2.8 V
Minimum supply voltage (Vsup)2.2 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
HY62UF16201A/ HY62QF16201A/ HY62EF16201A/
HY62SF16201A Series
128Kx16bit full CMOS SRAM
PRELIMINARY
DESCRIPTION
The HY62UF16201A / HY62QF16201A /
HY62EF16201A / HY62SF16201A is a high
speed, super low power and 2Mbit full CMOS
SRAM organized as 131,072 words by 16bits. The
HY62UF16201A
/
HY62QF16201A
/
HY62EF16201A / HY62SF16201A uses high
performance full CMOS process technology and
is designed for high speed and low power circuit
technology. It is particularly well-suited for the
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 1.5V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(LL/SL-part)
- 1.5V(min) data retention
Standard pin configuration
- 48ball CSP
Product
Voltage
Speed
Operation
Standby Current(uA)
No.
(V)
(ns)
Current(mA)
LL
SL
HY62UF16201A
3.0
55/70/85
15
10
2
HY62UF16201A-I
3.0
55/70/85
15
10
2
HY62QF16201A
2.5
70/85/100
10
10
2
HY62QF16201A-I
2.5
70/85/100
10
10
2
HY62EF16201A
2.0
85/100/120
10
10
2
HY62EF16201A-I
2.0
85/100/120
10
10
2
HY62SF16201A
1.8
100/120/150
10
10
2
HY62SF16201A-I
1.8
100/120/150
10
10
2
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Temperature
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
(Top View )
ADD INPUT
BUFFER
A1,A2
A4, A6~A7
A9
BLOCK DIAGRAM
SENSE AMP
ROW
DECODER
I/O1
PRE-DECODER
IO9 /UB A3
IO10 IO11 A5
Vss IO12 NC
Vcc IO13 NC
A4
A6
A7
/CS IO1
IO2 IO3
IO4 Vcc
A13
A14
A0
A3
A5
A11
/CS
/OE
/LB
/UB
/WE
ADD INPUT
BUFFER
BLOCK
DECODER
MEMORY ARRAY
512x128x32
WRITE DRIVER
A10
ADD INPUT
BUFFER
OUTPUT
BUFFER
A15~A16
A8
COLUMN
DECODER
/LB
/OE A0
A1
A2
NC
A12
I/O8
I/O9
A16 IO5 Vss
I/O16
IO15 IO14 A14 A15 IO6 IO7
IO16 NC
NC
A8
A12 A13 /WE IO8
A9
A10 A11 NC
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Funtion
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A16
Vcc
Vss
NC
Pin Funtion
Data Input/Output
Address Input
Power(3.0V/2.5V/2.0V/1.8V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.01 /Feb. 99
Hyundai Semiconductor
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