70V3569S5DRGI8 datasheet, PDF - EEWORLD Datasheet

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70V3569S5DRGI8: DescriptionDual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208; Categorystorage storage; File Size181KB，17 Pages; ManufacturerIDT (Integrated Device Technology)

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70V3569S5DRGI8 Overview

Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208

70V3569S5DRGI8 Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
package instruction	FQFP,
Reach Compliance Code	compliant
Maximum access time	5 ns
Other features	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
JESD-30 code	S-PQFP-G208
JESD-609 code	e3
length	28 mm
memory density	589824 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Number of functions	1
Number of terminals	208
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16KX36
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Parallel/Serial	PARALLEL
Maximum seat height	4.1 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm

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HIGH-SPEED 3.3V 16K x 36

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

IDT70V3569S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 4.2/5/6ns (max.)

– Industrial: 5ns (max)

Pipelined output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

– Fast 4.2ns clock to data out

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

◆

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-ball fine-pitch Ball Grid Array, and 256-pin Ball

Grid Array

Green parts availble, see ordering instructions

Functional Block Diagram

R/W

B B

3 3

L R

2 1

R/W

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

16K x 36

MEMORY

ARRAY

I/O

- I/O

35L

Din_L

Din_R

I/O

- I/O

35R

CLK

13L

CNTRST

ADS

CNTEN

CLK

Counter/

Address

Reg.

13R

ADDR_L

ADDR_R

Counter/

Address

Reg.

CNTRST

ADS

CNTEN

4831 tbl 01

OCTOBER 2014

DSC 4831/13

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Description	Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208	Multi-Port SRAM, 16KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM, 1 MM PITCH, GREEN, BGA-256	Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208	Dual-Port SRAM, 16KX36, 4.2ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208	Multi-Port SRAM, 16KX36, 5ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM, 0.80 MM PITCH, GREEN, FPBGA-208	Dual-Port SRAM, 16KX36, 6ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208	Multi-Port SRAM, 16KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM, 1 MM PITCH, GREEN, BGA-256
package instruction	FQFP,	LBGA, BGA256,16X16,40	FQFP,	FQFP,	LFBGA, BGA208,17X17,32	FQFP,	LBGA, BGA256,16X16,40
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
Maximum access time	5 ns	5 ns	5 ns	4.2 ns	5 ns	6 ns	5 ns
Other features	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE	PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
JESD-30 code	S-PQFP-G208	S-PBGA-B256	S-PQFP-G208	S-PQFP-G208	S-PBGA-B208	S-PQFP-G208	S-PBGA-B256
JESD-609 code	e3	e1	e3	e3	e1	e3	e1
length	28 mm	17 mm	28 mm	28 mm	15 mm	28 mm	17 mm
memory density	589824 bit	589824 bit	589824 bit	589824 bit	589824 bit	589824 bit	589824 bit
Memory IC Type	DUAL-PORT SRAM	MULTI-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	MULTI-PORT SRAM	DUAL-PORT SRAM	MULTI-PORT SRAM
memory width	36	36	36	36	36	36	36
Number of functions	1	1	1	1	1	1	1
Number of terminals	208	256	208	208	208	208	256
word count	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words	16384 words
character code	16000	16000	16000	16000	16000	16000	16000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	70 °C	70 °C	85 °C	70 °C	70 °C
organize	16KX36	16KX36	16KX36	16KX36	16KX36	16KX36	16KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	LBGA	FQFP	FQFP	LFBGA	FQFP	LBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, FINE PITCH	GRID ARRAY, LOW PROFILE	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Maximum seat height	4.1 mm	1.7 mm	4.1 mm	4.1 mm	1.7 mm	4.1 mm	1.7 mm
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	MATTE TIN	Tin/Silver/Copper (Sn/Ag/Cu)	MATTE TIN	MATTE TIN	Tin/Silver/Copper (Sn/Ag/Cu)	MATTE TIN	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	GULL WING	BALL	GULL WING	GULL WING	BALL	GULL WING	BALL
Terminal pitch	0.5 mm	1 mm	0.5 mm	0.5 mm	0.8 mm	0.5 mm	1 mm
Terminal location	QUAD	BOTTOM	QUAD	QUAD	BOTTOM	QUAD	BOTTOM
width	28 mm	17 mm	28 mm	28 mm	15 mm	28 mm	17 mm
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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