XCR5064C-7PC44I datasheet, PDF

Datasheet> All Categories > XCR5064C-7PC44I

Preview

XCR5064C-7PC44I: Description64 Macrocell CPLD with Enhanced Clocking; File Size359KB，16 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

Download Datasheet View All

XCR5064C-7PC44I Overview

64 Macrocell CPLD with Enhanced Clocking

Preview

Download Datasheet

View All

xcr5064c.fm Page 1 Tuesday, February 15, 2000 3:51 PM

APPLICATION NOTE

XCR5064C: 64 Macrocell CPLD with

Enhanced Clocking

14*

DS044 (v1.1) February 10, 2000

Product Specification

speed and zero power in a 64 macrocell CPLD. With the

FZP design technique, the XCR5064C offers true pin-to-pin

speeds of 7.5 ns, while simultaneously delivering power

that is less than 100

A at standby without the need for

`turbo bits' or other power down schemes. By replacing

conventional sense amplifier methods for implementing

product terms (a technique that has been used in PLDs

since the bipolar era) with a cascaded chain of pure CMOS

gates, the dynamic power is also substantially lower than

any competing CPLDz. These devices are the first TotalC-

MOS PLDs, as they use both a CMOS process technology

and

the patented full CMOS FZP design technique.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 2.0 ns,

regardless of the number of PLA product terms used, which

results in worst case t

's of only 9.5 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR5084C CPLDs are supported by industry stan-

dard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses Xilinx developed tools including WebFITTER.

The XCR5064C CPLD is reprogrammable using industry

standard device programmers from vendors such as Data

I/O, BPMicrosystems, SMS, and others. The XCR5064C

also includes an industry-standard, IEEE 1149.1, JTAG

interface through which In-System Programming (ISP) and

reprogramming of the device are supported.

Features

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

High speed pin-to-pin delays of 7.5 ns

Ultra-low static power of less than 100

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

Up to 12 clocks with programmable polarity at every

macrocell

5V, In-System Programmable (ISP) using a JTAG

interface

- On-chip supervoltage generation

- ISP commands include: Enable, Erase, Program,

Verify

- Supported by multiple ISP programming platforms

Four

pin JTAG interface (TCK, TMS, TDI, TDO)

- JTAG commands include: Bypass, Idcode

Support for complex asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5

CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

- Up to two asynchronous clocks

Programmable global 3-state pin facilitates "bed of

nails" testing without using logic resources

Available in PLCC and VQFP packages

Available in both Commercial and Industrial grades

•

Description

The XCR5064C CPLD (Complex Programmable Logic

Device) is the second in a family of CoolRunner™ CPLDs

from Xilinx Semiconductors. These devices combine high

DS044 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

Recommended Resources

Large range 7~40V to 5VDC-DC step-down circuit diagram

Half-point time-stopping circuit g

Low temperature alarm circuit

Can type FM radio circuit diagram

One control ten motor starting circuit_1

555 water level controller

Matlab Courseware: A very good set of Matlab courseware...; yanghaibo1121 FPGA/CPLD

The Temptation of 50 Oceans - Technical Analysis of th2822: [b][color=#5E7384]This content is originally created by [size=3]fickle[/size], a netizen of EEWORLD forum. If you need to reprint or use it for commercial purposes, you must obtain the author's consen...; fickle Industrial Control Electronics

TI M4 development board trial week plan jobszheng5: jobszheng5 M4 development board trial week plan submitted. It is divided into 4 small projects. The attached word document starts from the second page to explain the preparation of the project in deta...; jobszheng5 Microcontroller MCU

LM3S811 Timer Settings: void time_init() { SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); //Enable timer// SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1); // SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2); TimerConfigure(TIMER0_B...; 淮海的大学 Microcontroller MCU

How to turn pages when AT24C02 saves addresses?: There is an error in saving the 9th data. Please help....; ssc564023652 51mcu

XC886/888CLM: 8-bit microcontrollers with advanced networking capabilities: XC886/888CLM: 8-bit microcontroller with advanced network functions, integrated CAN controller and support for LIN, using the high-performance XC800 core based on the industry-standard 8051 architectu...; frozenviolet Industrial Control Electronics

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components