Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed,
µP-compatible
A/D converter
with track/hold function
ADC0820
DESCRIPTION
By using a half-flash conversion technique, the 8-bit ADC0820
CMOS A/D offers a 1.5µs conversion time while dissipating a
maximum 75mW of power. The half-flash technique consists of 31
comparators, a most significant 4-bit ADC and a least significant
4-bit ADC.
The input to the ADC0820 is tracked and held by the input sampling
circuitry, eliminating the need for an external sample-and-hold for
signals slewing at less than 100mV/µs.
For ease of interface to microprocessors, the ADC0820 has been
designed to appear as a memory location or I/O port without the
need for external interfacing logic.
PIN CONFIGURATION
D, F, N Packages
V
IN
1
20
19
18
17
16
15
14
13
12
11
TOP VIEW
V
DD
NC
OFL
DB7
DB6
DB5
DB4
CS
V
REF
(+)
V
REF
(–)
DB0 2
DB1 3
DB2 4
DB3 5
WR/RDY
MODE
RD
INT
6
7
8
9
10
FEATURES
GND
•
Built-in track-and-hold function
•
No missing codes
•
No external clocking
•
Single supply—5V
DC
•
Easy interface to all microprocessors, or operates stand-alone
•
Latched 3-State outputs
•
Logic inputs and outputs meet both MOS and TTL voltage level
specifications
APPLICATIONS
•
Operates ratiometrically or with any reference value equal to or
•
0V to 5V analog input voltage range with single 5V supply
•
No zero- or full-scale adjust required
•
Overflow output available for cascading
•
0.3″ standard width 20-pin DIP
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dual In-Line Package (DIP)
20-Pin Plastic Small Outline (SO) package
less than V
DD
•
Microprocessor-based monitoring and control systems
•
Transducer/µP interface
•
Process control
•
Logic analyzers
•
Test and measurement
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
ORDER CODE
ADC0820CNEN
ADC0820CNED
DWG #
0408B
1021B
August 31, 1994
568
853-1631 13721
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed,
µP-compatible
A/D converter with
track/hold function
ADC0820
BLOCK DIAGRAM
V
REF
(+)
OFL
4–BIT
FLASG
ADC
(4MSBs)
OFL
DB7
DB6
DB5
DB4
V
REF
(–)
V
IN
V
REF
(+)
–
∑
+
4–BIT
DAC
V
REF
(–)
V
REF
(+)
16
OUTPUT
LATCH
AND
THREE–STATE
BUFFERS
4–BIT
FLASG
ADC
(4LSBs)
DB3
DB2
DB1
DB0
V
REF
(–)
TIMING AND CONTROL CIRCUITRY
INT
MODE
WR/RDY
CS
RD
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
SYMBOL
V
IN
DB0
DB1
DB2
DB3
WR/RDY
Analog input; range=GND≤V
IN
≤V
DD
3-state data output—Bit 0 (LSB)
3-state data output—Bit 1
3-state data output—Bit 2
3-state data output—Bit 3
DESCRIPTION
WR-RD Mode
WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time
out, t
I
) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD
does not occur prior to this time out (see Figures 3a and 3b).
RD Mode
RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will
go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a
microprocessor system (see Figure 1).
7
Mode
Mode: Mode selection input—it is internally tied to GND through a 30µA current source.
RD Mode: When mode is Low.
WR-RD Mode: When mode is High.
8
RD
WR-RD Mode
With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to
increase the speed of the converter by reading data prior to the preset internal time out (T
I
~ 800ns). If this is done,
the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b).
RD Mode
With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the
completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see
Figure 1).
9
INT
WR-RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go
Low ~ 800ns (the preset internal time out, t
I
) after the rising edge of WR (see Figure 3a); or INT will go Low after
the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of
RD or CS (see Figures 3a and 3b).
August 31, 1994
569
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed,
µP-compatible
A/D converter with
track/hold function
ADC0820
PIN DESCRIPTION
(Continued)
PIN NO
SYMBOL
DESCRIPTION
RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT is reset by
the rising edge of RD or CS (see Figure 1).
10
11
12
13
14
15
16
17
18
GND
V
REF
(-)
V
REF
(+)
CS
DB4
DB5
DB6
DB7
OFL
Ground
The bottom of resistor ladder, voltage range: GND≤V
REF
(-)≤V
REF
(+)
The top of resistor ladder, voltage range: V
REF
(-)≤V
REF
(+)≤V
DD
.
CS must be Low in order for the RD or WR to be recognized by the converter.
3-State data output—Bit 4
3-State data output—Bit 5
3-State data output—Bit 6
3-State data output—Bit 7 (MSB)
Overflow output—if the analog input is higher than the V
REF
(+)- LSB, OFL will be low at the end of conversion. It can
be used to cascade 2 or more devices to have more resolution (9, 10-bit). It is always active and never becomes
3-state.
No connection
Power supply voltage
19
20
NC
V
DD
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
DD
Supply voltage
Logic control inputs
Voltage at other inputs and output
T
STG
P
D
Storage temperature range
Maximum power dissipation
3
T
A
=25°C(still-air)
N package
D package
T
SOLD
T
A
Lead temperature (soldering, 10sec)
Operating ambient temperature range
ADC0820CNEN/CNED
NOTES:
1. Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.
2. All voltages are measured with respect to GND, unless otherwise specified.
3. Derate above 25°C at the following rates:
N package at 13.5mW/°C
D package at 11.1mW/°C
1690
1390
300
T
MIN
≤T
A
≤T
MAX
0 to +70
°C
mW
mW
°C
PARAMETER
RATING
7
-0.2 to V
DD
+0.2
-0.2 to V
DD
+0.2
-65 to +150
UNIT
V
V
V
°C
August 31, 1994
570
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed,
µP-compatible
A/D converter with
track/hold function
ADC0820
DC ELECTRICAL CHARACTERISTICS
RD mode (Pin 7=0), V
DD
=5V, V
REF
(+)=5V, and V
REF
(-)=GND, unless otherwise specified. Limits apply from T
MIN
to T
MAX
.
SYMBOL
Resolution
Unadjusted error
1
R
REF
V
REF
(+)
V
REF
(-)
V
IN
Reference resistance
Input
Input
voltage
5
voltage
5
CS=V
DD
V
IN
=V
DD
V
IN
=GND
V
DD
=5V±5%
V
DD
=5.25V
V
DD
=4.75V
CS, WR, RD
Mode
CS, WR, RD
Mode
2.0
3.5
GND
GND
Input voltage
ADC0820C
1
V
REF
(-)
GND
GND-0.1
-3
±1/16
1.6
PARAMETER
TEST CONDITIONS
LIMITS
Min
8
Typ
3
8
Max
8
±1
4
V
DD
V
REF
(+)
V
DD
+0.1
3
±1/4
V
DD
V
DD
0.8
1.5
1
3
30
-1
2.4
4.5
4.6
4.74
V
200
µA
µA
UNIT
bits
LSB
kΩ
V
V
V
µA
LSB
V
V
Maximum analog input leakage current
Power supply sensitivity
V
IN(1)
V
IN(0)
Logical “1” input voltage
Logical “0” input voltage
V
IN(1)
=5V; CS, RD
I
IN(1)
I
IN(0)
Logical “1” input current
Logical “0” input current
V
IN(1)
=5V; WR
V
IN(1)
=5V; Mode
V
IN(0)
=0V; CS, RD, WR, Mode
V
DD
=4.75V, I
OUT
=-360µA;
V
OUT(1)
Logical “1” output voltage
DB0-DB7, OFL, INT
V
DD
=4.75V, I
OUT
=-10µA
DB0-DB7, OFL, INT
V
OUT(0)
Logical “0” output voltage
V
DD
=4.75V, I
OUT
=1.6mA;
DB0-DB7, OFL, INT, RDY
V
OUT
=5V; DB0-DB7, RDY
I
OZ
3-state output current
V
OUT
=0V; DB0-DB7, RDY
V
OUT
=0V, DB0-DB7, OFL
I
SOURCE
I
SINK
I
DD
V
DD
Output source current
INT
Output sink current
Supply current
Range
V
OUT
=5V; DB0-DB7, OFL, INT, RDY
CS=WR=RD=0
4.5
4.5
7
8
20
6
-3
6
12
0.2
0.4
3
V
µA
mA
mA
15
5.5
mA
V
August 31, 1994
571
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed,
µP-compatible
A/D converter with
track/hold function
ADC0820
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5V, t
R
= t
F
= 20ns, V
REF(+)
= 5V, V
REF(-)
= 0V, and T
A
= 25°C, unless otherwise specified.
SYMBOL
t
CRD
t
ACCO
t
CWR-RD
t
WR
t
RD
t
ACC1
PARAMETER
Conversion time for RD mode
Access time (delay from falling edge of
RD to output valid)
Conversion time for WR-RD mode
Write time
Read time
Min
Max
Min
TEST CONDITIONS
Mode=0, Figure 1
Mode=0, Figure 1
Mode=V
DD
, t
WR
=600ns, t
RD
=600ns;
Figures 3a and 3b
Mode=V
DD
, Figures 3a and 3b
2
Mode=V
DD
, Figures 3a and
Mode=V
DD
, t
RD
<t
I
;
Figure 3b, C
L
=15pF
C
L
=100pF
Mode=V
DD
, t
RD
>t
I
;
Figure 3a, C
L
=15pF
C
L
=100pF
t
I
t
1H
, t
0H
t
INTL
t
INTH
t
INTHWR
t
RDY
t
ID
t
RI
t
P
SR
C
VIN
C
OUT
C
IN
Internal comparison time
Three-state control (delay from rising
edge of RD to Hi-Z state)
Delay from rising edge of WR to falling
edge of INT
Delay from rising edge of RD to rising
edge of INT
Delay from rising edge of WR to rising
edge of INT
Delay from CS to RDY
Delay from INT to output valid
Delay from RD to INT
Delay from end of conversion to next
conversion
Slew rate, tracking
Analog input capacitance
Logic output capacitance
Logic input capacitance
Mode=V
DD
;
Figures 2 and 3a, C
L
=50pF
R
L
=1kΩ, C
L
=10pF
Mode=V
DD
, C
L
=50pF
t
RD
>t
I
; Figure 3a
t
RD
<t
I
; Figure 3b
Figures 1, 3a, and 3b,
C
L
=50pF
Figure 2, C
L
=50pF
Figure 1, C
L
=50pF, Mode=0
Figure 2
Mode=V
DD
, t
RD
<t
I
;
Figure 3b
Figures 1, 2, 3a, and 3b
2
500
0.1
45
5
5
3b
2
600
50
600
190
210
70
90
800
100
280
320
120
150
1300
200
ns
ns
ns
ns
LIMITS
4
Min
Typ
3
1.6
t
CRD
+20
Max
2.5
t
CRD
+50
1.52
UNIT
µs
ns
µs
ns
µs
ns
ns
Access time (delay from falling edge of
RD t o output valid)
Access time (delay from falling edge of
RD t o output valid)
t
ACC2
t
RD
+200
125
175
50
20
200
t
I
t
RD
+290
225
270
100
50
290
ns
ns
ns
ns
ns
ns
ns
ns
V/µs
pF
pF
pF
NOTES:
1. Unadjusted error includes offset, full-scale, and linearity errors.
2. Accuracy may degrade if t
WR
or t
RD
is shorter than the minimum value specified.
3. Typical values are at 25°C and represent most likely parametric norm.
4. Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
5. V
REF
and VIN must be applied after V
CC
has been turned on to prevent possibility of latching.
August 31, 1994
572
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