DM5430J datasheet, PDF - EEWORLD Datasheet

DM5430J: DescriptionIC TTL/H/L SERIES, 8-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate; Categorylogic logic; File Size101KB，4 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM5430J Overview

IC TTL/H/L SERIES, 8-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	National Semiconductor（TI ）
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
series	TTL/H/L
JESD-30 code	R-GDIP-T14
JESD-609 code	e0
length	19.43 mm
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.016 A
Number of functions	1
Number of entries	8
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	6 mA
Prop。Delay @ Nom-Sup	22 ns
propagation delay (tpd)	15 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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