5. Please refer to failure rates in reliability data
sheet to assess the reliability impact of
running devices above a channel temperature
of 140°C.
6. Thermal resistance measured using 150°C
Liquid Crystal Measurement method.
500
+0.6 V
400
I
DS
(mA)
300
0V
200
100
-0.6 V
0
0
2
4
V
DS
(V)
6
8
Figure 1. Typical Pulsed I-V Curves
[7]
.
(V
GS
= -0.2 V per step)
Note:
7. Under large signal conditions, V
GS
may swing
positive and the drain current may exceed
I
dss
. These conditions are acceptable as long
as the Maximum P
diss
and P
in max
ratings are
not exceeded.
Product Consistency Distribution Charts
[8, 9]
100
Cpk = 1.05
Stdev = 0.07
80
120
150
Cpk = 1.00
Stdev = 1.07
120
100
80
Cpk = 4.37
Stdev = 1.11
60
-3 Std
40
+3 Std
90
-3 Std
60
40
+3 Std
60
-3 Std
+3 Std
20
30
20
0
28
30
32
OIP3 (dBm)
34
36
13
14
15
GAIN (dB)
16
17
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NF (dBm)
0
Figure 2. NF @ 2 GHz, 4 V, 60 mA.
LSL = 28.5, Nominal = 0.6, USL = 0.8.
Figure 3. OIP3 @ 2 GHz, 4 V, 60 mA.
LSL = 28.5, Nominal = 31.0, USL = 36.0
Figure 4. Gain @ 2 GHz, 4 V, 60 mA.
LSL = 13.5, Nominal = 15.0, USL = 16.5
Notes:
8. Distribution data sample size is 349 samples from 4 different wafers. Future wafers allocated to this product may have nominal values anywhere within
the upper and lower spec limits.
9. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based on
production test requirements. Circuit losses have been de-embedded from actual measurements.
2
ATF-331M4 DC Electrical Specifications
T
A
= 25°C, RF parameters measured in a test circuit for a typical device
Symbol Parameter and Test Condition
Idss
[1]
Vp
[1]
Id
Gm
[1]
Igdo
Igss
NF
Ga
OIP3
P1dB
Saturated Drain Current
Pinch-off Voltage
Quiescent Bias Current
Transconductance
Gate to Drain Leakage Current
Gate Leakage Current
Noise Figure
Associated Gain
Output 3
rd
Order
Intercept Point
[3]
1dB Compressed
Output Power
[3]
f = 2 GHz
f = 900 MHz
f = 2 GHz
f = 900 MHz
f = 2 GHz, 5 dBm Pout/Tone
f = 900 MHz, 5 dBm Pout/Tone
f = 2 GHz
f = 900 MHz
Vds = 1.5 V, Vgs = 0V
Vds = 1.5 V, Ids = 10% of Idss
Vgs = -0.51 V, Vds = 4V
Vds = 1.5 V, Gm = Idss/Vp
Vgd = -5 V
Vgd = Vgs = -4V
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Vds = 4 V, Ids = 60 mA
Units
mA
V
mA
mmho
µA
µA
dB
dB
dB
dB
dBm
dBm
dBm
dBm
Min.
175
-0.65
—
360
—
—
—
—
13.5
—
28.5
—
—
—
Typ.
[2]
237
-0.5
60
440
—
42
0.6
0.5
15
21
31
30.8
19
18
Max.
305
-0.35
—
—
1000
600
0.8
—
16.5
—
—
—
—
—
Notes:
1. Guaranteed at wafer probe level
2. Typical values are determined from a sample size of 349 parts from 4 wafers.
3. Measurements obtained using production test board described in Figure 5.
Input
50Ω Input
Transmission Line
Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag
= 0.13
Γ_ang
= 113°
(0.3 dB loss)
DUT
50Ω Output
Transmission Line
Including
Gate Bias T
(0.5 dB loss)
Output
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit
represents a trade-off between an optimal noise match and a realizable match based on production test requirements. Circuit losses have been
de-embedded from actual measurements.
3
ATF-331M4 Typical Performance Curves
40
2V
3V
4V
40
2V
3V
4V
25
2V
3V
4V
20
30
30
OIP3, IIP3 (dBm)
OIP3, IIP3 (dBm)
P1dB (dBm)
0
20
40
60
80
100
15
20
20
10
10
10
5
0
0
20
40
60
80
100
I
ds
(mA)
0
I
ds
(mA)
0
0
20
40
60
80
100
I
dsq
(mA)
Figure 6. OIP3, IIP3 & Bias
[1]
at 2 GHz.
Figure 7. OIP3, IIP3 & Bias
[1]
at 900 MHz.
Figure 8. P1dB vs. Bias
[1,2]
2 GHz.
25
20
2V
3V
4V
16
15
14
2V
3V
4V
1.4
1.2
22
21
2V
3V
4V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
120
NOISE FIGURE (dB)
P1dB (dBm)
1.0
0.8
0.6
0.4
0.2
100
20
15
13
12
19
18
17
16
0
20
40
60
I
d
(mA)
80
100
10
5
11
10
0
20
40
60
80
100
0
20
40
I
d
(mA)
60
80
I
dsq
(mA)
0
Figure 9. P1dB vs. Bias
[1]
900 MHz.
Figure 10. NF & Gain vs. Bias
[1]
at 2 GHz.
Figure 11. NF & Gain vs. Bias
[1]
at 900 MHz.
Notes:
1. Measurements made on fixed tuned
production test board that was tuned for
optimal gain match with reasonable noise
figure at 4V 60 mA bias. This circuit
represents a trade-off between an optimal
noise match, maximum gain match and a
realizable match based on production test
board requirements. Circuit losses have been
de-embedded from actual measurements.
2. Quiescent drain current, Idsq, is set with zero
RF drive applied. As P1dB is approached, the
drain current may increase or decrease
depending on frequency and dc bias point. At
lower values of Idsq the device is running
closer to class B as power output approaches
P1dB. This results in higher P1dB and higher
PAE (power added efficiency) when compared
to a device that is driven by a constant
current source as is typically done with active
biasing.
4
NOISE FIGURE (dB)
GAIN (dB)
GAIN (dB)
ATF-331M4 Typical Performance Curves,
continued
1.6
1.4
1.2
GAIN (dB)
GAIN (dB)
Fmin (dB)
30
25
25
85°C
25°C
-40°C
2.0
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
FREQUENCY (GHz)
20
15
10
10
5
0
0
2
4
6
8
10
FREQUENCY (GHz)
5
0
2
4
FREQUENCY (GHz)
6
8
0
0.5
15
1.0
Figure 12. Fmin vs. Frequency at 4 V, 60 mA.
Figure 13. Associated Gain vs. Frequency
at 4V, 60 mA.
35
OIP3, P1dB (dBm), GAIN (dB)
Figure 14. Fmin & Ga vs. Frequency and Temp.
Vd = 4V, Ids = 60 mA.
3.5
OIP3, P1dB (dBm), GAIN (dB)
35
30
P1dB, OIP3 (dBm)
35
30
25
20
15
10
5
0
P1dB
OIP3
Gain
NF
3.5
3.0
NOISE FIGURE (dB)
30
25
20
15
10
5
0
3.0
NOISE FIUGRE (dB)
P1dB
OIP3
2.5
Gain
NF
25
20
15
10
5
0
85°C
25°C
-40°C
2.5
2.0
1.5
1.0
0.5
2.0
1.5
1.0
0.5
0
100
0
1
2
3
4
5
6
7
8
0
20
40
60
80
0
20
40
60
80
0
100
FREQUENCY (GHz)
I
dsq
(mA)
I
dsq
(mA)
Figure 15. P1dB, OIP3 vs. Frequency and
Temp at Vd = 4V, Ids = 60 mA.
Figure 16. OIP3, P1dB, NF and Gain vs.
Bias
[1,2]
at 3.9 GHz.
Figure 17. OIP3, P1dB, NF at 5.8 GHz.
Notes:
1. Measurements made on fixed tuned
production test board that was tuned for
optimal gain match with reasonable noise
figure at 4V 60 mA bias. This circuit
represents a trade-off between an optimal
noise match, maximum gain match and a
realizable match based on production test
board requirements. Circuit losses have been
de-embedded from actual measurements.
2. Quiescent drain current, Idsq, is set with zero
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