M29F080A
8 Mbit (1Mb x8, Uniform Block) Single Supply Flash Memory
PRELIMINARY DATA
s
SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 70ns
PROGRAMMING TIME
– 8µs by Byte typical
44
s
s
s
s
16 UNIFORM 64 Kbyte MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
TSOP40 (N)
10 x 20mm
SO44 (M)
1
s
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
s
TEMPORARY BLOCK UNPROTECTION
MODE
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F1h
A0-A19
W
E
G
RP
M29F080A
RB
VCC
s
s
20
8
DQ0-DQ7
s
s
VSS
AI00501C
January 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/22
M29F080A
Figure 2A. TSOP Connections
Figure 2B. SO Connections
NC
RP
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
VSS
VSS
1
44
2
43
3
42
4
41
5
40
6
39
7
38
37
8
9
36
10
35
11
34
M29F080A
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
AI00521B
A19
A18
A17
A16
A15
A14
A13
A12
E
VCC
NC
RP
A11
A10
A9
A8
A7
A6
A5
A4
1
40
10
11
M29F080A
31
30
20
21
AI00520B
NC
NC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
VCC
E
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
Table 1. Signal Names
A0-A19
DQ0-DQ7
E
G
W
RP
RB
V
CC
V
SS
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground
Not Connected Internally
SUMMARY DESCRIPTION
The M29F080A is an 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory
2/22
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected in groups to prevent accidental Program
or Erase commands from modifying the memory.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in a TSOP40 (10 x 20mm)
and SO44 packages. Access times of 70ns, 90ns
and 120ns are available. The memory is supplied
with all the bits erased (set to ’1’).
M29F080A
Table 2. Absolute Maximum Ratings
(1)
Symbol
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
T
A
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Value
0 to 70
–40 to 85
–40 to 125
–50 to 125
–65 to 150
–0.6 to 6
–0.6 to 6
–0.6 to 13.5
Unit
°C
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 14 and Figure 10, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14 and Figure
10, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
3/22
M29F080A
Table 3. Block Addresses
Size
(Kbytes)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address Range
F0000h-FFFFFh
7
E0000h-EFFFFh
D0000h-DFFFFh
6
C0000h-CFFFFh
B0000h-BFFFFh
5
A0000h-AFFFFh
90000h-9FFFFh
4
80000h-8FFFFh
70000h-7FFFFh
3
60000h-6FFFFh
50000h-5FFFFh
2
40000h-4FFFFh
30000h-3FFFFh
1
20000h-2FFFFh
10000h-1FFFFh
0
00000h-0FFFFh
Protection
Group
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 7B, Read Mode AC Waveforms,
and Table 11B, Read AC Characteristics, for de-
tails of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 8 and 9, Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
4/22
M29F080A
Table 4. Bus Operations
Operation
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Note: X = V
IL
or V
IH
.
E
V
IL
V
IL
X
V
IH
V
IL
V
IL
G
V
IL
V
IH
V
IH
X
V
IL
V
IL
W
V
IH
V
IL
V
IH
X
V
IH
V
IH
Address Inpu ts
Cell Address
Command Address
X
X
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Data
Inputs/Outpu ts
Data Output
Data Input
Hi-Z
Hi-Z
20h
F1h
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
When Chip Enable is at V
IH
the Supply Current is
reduced to the TTL Standby Supply Current, I
CC2
.
To further reduce the Supply Current to the CMOS
Standby Supply Current, I
CC3
, Chip Enable should
be held within V
CC
±
0.2V. For Standby current
levels see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC4
, for Program or Erase operations un-
til the operation completes.
Automatic Standby.
If CMOS levels (V
CC
±
0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC3
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 4, Bus Operations.
Block Protection
and
Blocks Unprotection.
Blocks
can be protected in groups against accidental Pro-
gram or Erase. See Table 3, Block Addresses, for
details of which blocks must be protected together
as a group. Protected blocks can be unprotected
to allow data to be changed. Block Protection and
Block Unprotection operations must only be per-
formed on programming equipment.
For further information refer to Application Note
AN1122, Applying Protection and Unprotection to
M29 Series Flash.
5/22
ADI Reference Circuit
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