0
R
XC95288XL High Performance
CPLD
0
5
DS055 (v1.5) June 20, 2002
Product Specification
propagation delays of 6 ns. See
Figure 2
for architecture
overview.
Features
•
•
•
•
6 ns pin-to-pin logic delays
System frequency up to 208 MHz
288 macrocells with 6,400 usable gates
Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HS
(0.175*PT
HS
+ 0.345) + MC
LP
(0.052*PT
LP
+ 0.272) + 0.04 * MC
TOG
(MC
HS
+MC
LP
)* f
where:
MC
HS
= # macrocells in high-speed configuration
PT
HS
= average number of high-speed product terms
per macrocell
MC
LP
= # macrocells in low power configuration
PT
LP
= average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
Figure 1
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note
XAPP114, “Understanding XC9500XL
CPLD Power.”
550
500
450
•
•
•
•
•
•
208 MHz
Typical ICC (mA)
400
350
300
250
200
150
100
50
0
hP
Hig
or
e
rf
ma
n ce
•
P
Low
ow
er
94 MHz
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
50
100
150
200
250
Clock Frequency (MHz)
DS055_01_121501
Figure 1:
Typical I
CC
vs. Frequency for XC95288XL
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS055 (v1.5) June 20, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1
R
XC95288XL High Performance CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
T
J
Description
Supply voltage relative to GND
Input voltage relative to GND
(1)
Voltage applied to 3-state output
(1)
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
Value
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+260
+150
Units
V
V
V
o
C
o
C
o
C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
V
CCINT
V
CCIO
V
IL
V
IH
V
O
Parameter
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to 70
o
C
Industrial T
A
= –40
o
C to +85
o
C
Min
3.0
3.0
3.0
2.3
0
2.0
0
Max
3.6
3.6
3.6
2.7
0.80
5.5
V
CCIO
Units
V
V
V
V
V
V
V
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
High-level input voltage
Output voltage
Quality and Reliability Characteristics
Symbol
T
DR
N
PE
V
ESD
Data Retention
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
Parameter
Min
20
10,000
2,000
Max
-
-
-
Units
Years
Cycles
Volts
DC Characteristic Over Recommended Operating Conditions
Symbol
V
OH
V
OL
I
IL
I
IH
I
IH
Parameter
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
I/O high-Z leakage current
I/O high-Z leakage current
Test Conditions
I
OH
= –4.0 mA
I
OH
= –500
µA
I
OL
= 8.0 mA
I
OL
= 500
µA
V
CC
= Max; V
IN
= GND or V
CC
V
CC
= Max; V
IN
= GND or V
CC
V
CC
= Max; V
CCIO
= Max;
V
IN
= GND or 3.6V
V
CC
Min < V
IN
< 5.5V
C
IN
I
CC
I/O capacitance
Operating supply current
(low power mode, active)
V
IN
= GND; f = 1.0 MHz
V
IN
= GND, No load; f = 1.0 MHz
Min
2.4
90% V
CCIO
-
-
-
-
-
-
-
85 (Typical)
Max
-
-
0.4
0.4
±10
±10
±10
±50
10
Units
V
V
V
V
µA
µA
µA
µA
pF
mA
DS055 (v1.5) June 20, 2002
Product Specification
www.xilinx.com
1-800-255-7778
3
R
XC95288XL High Performance CPLD
Internal Timing Parameters
XC95288XL-6
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable
delay
Product Term Control Delays
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
LOGI
T
LOGILP
T
F
T
PTA
T
PTA2
T
SLEW
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
2.0
1.0
6.2
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
-
-
-
-
-
-
2.2
1.2
2.2
4.5
2.4
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC95288XL-7
Min
Max
XC95288XL-10
Min
Max
Units
Internal Register and Combinatorial Delays
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
Fast CONNECT II feedback delay
-
2.0
1.6
2.0
1.6
-
-
6.0
-
-
-
1.0
5.5
1.6
0.4
-
-
-
-
0.2
6.2
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
-
1.4
6.4
3.5
1.3
-
-
-
-
0.5
6.4
-
3.0
3.5
3.0
3.5
-
-
10.0
-
-
-
1.8
7.3
4.2
1.7
-
-
-
-
1.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Feedback Delays
Time Adders
Incremental product term allocator delay
(first incremental delay)
Incremental product term allocator delay
(subsequent incremental delay)
Slew-rate limited delay
-
-
-
0.8
0.3
3.5
-
-
-
0.8
0.3
4.0
-
-
-
1.0
0.4
4.5
ns
ns
ns
DS055 (v1.5) June 20, 2002
Product Specification
www.xilinx.com
1-800-255-7778
5
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