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XC95216-10PQ160I

Description
FLASH PLD, 10 ns, PQFP160
CategoryProgrammable logic devices    Programmable logic   
File Size60KB,10 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

XC95216-10PQ160I Overview

FLASH PLD, 10 ns, PQFP160

XC95216-10PQ160I Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerXILINX
Parts packaging codeQFP
package instructionPLASTIC, QFP-160
Contacts160
Reach Compliance Code_compli
ECCN codeEAR99
Other features216 MACROCELLS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency66.7 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G160
JESD-609 codee0
JTAG BSTYES
length28 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines133
Number of macro cells216
Number of terminals160
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize0 DEDICATED INPUTS, 133 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP160,1.2SQ
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)225
power supply3.3/5,5 V
Programmable logic typeFLASH PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height3.7 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width28 mm
Base Number Matches1
1
XC95216 In-System Programmable
CPLD
1
0*
August 21, 2001 (Version 3.1)
Product Specification
Features
10 ns pin-to-pin logic delays on all pins
f
CNT
to 111 MHz
216 macrocells with 4800 usable gates
Up to 166 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packages
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
shows a typical calculation for the XC95216
device.
600
erform
High P
ance
(500)
Typical I
CC
(mA)
400
(360)
(340)
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of twelve
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See
Figure 2
for the architec-
ture overview.
Low P
200
ower
0
50
Clock Frequency (MHz)
100
X5918
Figure 1: Typical I
CC
vs. Frequency For XC95216
August 21, 2001 (Version 3.1)
1
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