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EPF10K130VGC599-3

Description
Loadable PLD, 0.7ns, CMOS, CPGA599, CERAMIC, PGA-599
CategoryProgrammable logic devices    Programmable logic   
File Size640KB,128 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric View All

EPF10K130VGC599-3 Overview

Loadable PLD, 0.7ns, CMOS, CPGA599, CERAMIC, PGA-599

EPF10K130VGC599-3 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAltera (Intel)
Parts packaging codePGA
package instructionIPGA, SPGA599,47X47
Contacts599
Reach Compliance Codeunknown
ECCN code3A991
JESD-30 codeS-CPGA-P599
JESD-609 codee0
length62.484 mm
Humidity sensitivity level1
Dedicated input times4
Number of I/O lines470
Number of entries470
Number of logical units832
Output times466
Number of terminals599
Maximum operating temperature70 °C
Minimum operating temperature
organize4 DEDICATED INPUTS, 470 I/O
Output functionREGISTERED
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeIPGA
Encapsulate equivalent codeSPGA599,47X47
Package shapeSQUARE
Package formGRID ARRAY, INTERSTITIAL PITCH
Peak Reflow Temperature (Celsius)220
power supply3.3 V
Programmable logic typeLOADABLE PLD
propagation delay0.7 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width62.484 mm
Includes
FLEX 10KA
FLEX 10K
Embedded Programmable
Logic Device Family
Data Sheet
®
January 2003, ver. 4.2
Features...
The industry’s first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
integration
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
Logic array for general logic functions
High density
10,000 to 250,000 typical gates (see
Tables 1
and
2)
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
MultiVolt
TM
I/O interface support
5.0-V tolerant input pins in FLEX
®
10KA devices
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG)
PCI
Local Bus Specification, Revision 2.2
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM)
(1)
Maximum system gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
EPF10K10
EPF10K10A
10,000
31,000
576
72
3
6,144
150
EPF10K20
20,000
63,000
1,152
144
6
12,288
189
EPF10K30
EPF10K30A
30,000
69,000
1,728
216
6
12,288
246
EPF10K40
40,000
93,000
2,304
288
8
16,384
189
EPF10K50
EPF10K50V
50,000
116,000
2,880
360
10
20,480
310
Altera Corporation
DS-F10K-4.2
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