74AUP1T58GW datasheet, PDF - EEWORLD Datasheet

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74AUP1T58GW: DescriptionLow-power configurable gate with voltage-level translator; Categorylogic logic; File Size75KB，17 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74AUP1T58GW Overview

Low-power configurable gate with voltage-level translator

74AUP1T58GW Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOT-363
package instruction	PLASTIC, SOT-363, SC-88, PACKAGE-6
Contacts	6
Reach Compliance Code	compli
series	AUP/ULP/V
JESD-30 code	R-PDSO-G6
JESD-609 code	e3
length	2 mm
Load capacitance (CL)	30 pF
Logic integrated circuit type	LOGIC CIRCUIT
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of functions	1
Number of terminals	6
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP6,.08
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3 V
Prop。Delay @ Nom-Su	9.4 ns
Certification status	Not Qualified
Schmitt trigger	YES
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1.25 mm

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74AUP1T58

Low-power conﬁgurable gate with voltage-level translator

Rev. 02 — 29 September 2009

Product data sheet

1. General description

The 74AUP1T58 provides low-power, low-voltage conﬁgurable logic gate functions. The

output state is determined by eight patterns of 3-bit input. The user can choose the logic

functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to

or GND.

This device ensures a very low static and dynamic power consumption across the entire

range from 2.3 V to 3.6 V.

The 74AUP1T58 is designed for logic-level translation applications with input switching

levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single

2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from

3.6 V to 2.3 V.

This device is fully speciﬁed for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across

the entire V

range.

2. Features

Wide supply voltage range from 2.3 V to 3.6 V

High noise immunity

ESD protection:

HBM JESD22-A114F Class 3A exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Low static power consumption; I

= 1.5

µA

(maximum)

Latch-up performance exceeds 100 mA per JESD 78B Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V

OFF

circuitry provides partial Power-down mode operation

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and

−40 °C

to +125

°C

74AUP1T58GW Related Products

	74AUP1T58GW	74AUP1T58GF	74AUP1T58GM	74AUP1T58
Description	Low-power configurable gate with voltage-level translator	Low-power configurable gate with voltage-level translator	Low-power configurable gate with voltage-level translator	Low-power configurable gate with voltage-level translator
Source Url Status Check Date	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00	-
Is it lead-free?	Lead free	Lead free	Lead free	-
Is it Rohs certified?	conform to	conform to	conform to	-
Maker	NXP	NXP	NXP	-
Parts packaging code	SOT-363	SON	SON	-
package instruction	PLASTIC, SOT-363, SC-88, PACKAGE-6	1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, XSON-6	1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, XSON-6	-
Contacts	6	6	6	-
Reach Compliance Code	compli	compli	compli	-
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	-
JESD-30 code	R-PDSO-G6	S-PDSO-N6	R-PDSO-N6	-
JESD-609 code	e3	e3	e3	-
length	2 mm	1 mm	1.45 mm	-
Load capacitance (CL)	30 pF	30 pF	30 pF	-
Logic integrated circuit type	LOGIC CIRCUIT	LOGIC CIRCUIT	LOGIC CIRCUIT	-
MaximumI(ol)	0.004 A	0.004 A	0.004 A	-
Humidity sensitivity level	1	1	1	-
Number of functions	1	1	1	-
Number of terminals	6	6	6	-
Maximum operating temperature	125 °C	125 °C	125 °C	-
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TSSOP	VSON	VSON	-
Encapsulate equivalent code	TSSOP6,.08	SOLCC6,.04,14	SOLCC6,.04,20	-
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	-
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	-
method of packing	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	-
Peak Reflow Temperature (Celsius)	260	260	260	-
power supply	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	-
Prop。Delay @ Nom-Su	9.4 ns	9.4 ns	9.4 ns	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Schmitt trigger	YES	YES	YES	-
Maximum seat height	1.1 mm	0.5 mm	0.5 mm	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	-
Nominal supply voltage (Vsup)	3 V	3 V	3 V	-
surface mount	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	-
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	-
Terminal surface	Tin (Sn)	Tin (Sn)	Tin (Sn)	-
Terminal form	GULL WING	NO LEAD	NO LEAD	-
Terminal pitch	0.65 mm	0.35 mm	0.5 mm	-
Terminal location	DUAL	DUAL	DUAL	-
Maximum time at peak reflow temperature	30	30	30	-
width	1.25 mm	1 mm	1 mm	-

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