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74AUP1T58GF

Description
Low-power configurable gate with voltage-level translator
Categorylogic    logic   
File Size75KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74AUP1T58GF Overview

Low-power configurable gate with voltage-level translator

74AUP1T58GF Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSON
package instruction1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, XSON-6
Contacts6
Reach Compliance Codecompli
seriesAUP/ULP/V
JESD-30 codeS-PDSO-N6
JESD-609 codee3
length1 mm
Load capacitance (CL)30 pF
Logic integrated circuit typeLOGIC CIRCUIT
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of functions1
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Encapsulate equivalent codeSOLCC6,.04,14
Package shapeSQUARE
Package formSMALL OUTLINE, VERY THIN PROFILE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Su9.4 ns
Certification statusNot Qualified
Schmitt triggerYES
Maximum seat height0.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formNO LEAD
Terminal pitch0.35 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width1 mm
74AUP1T58
Low-power configurable gate with voltage-level translator
Rev. 02 — 29 September 2009
Product data sheet
1. General description
The 74AUP1T58 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to
V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T58 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
range.
2. Features
I
Wide supply voltage range from 2.3 V to 3.6 V
I
High noise immunity
I
ESD protection:
N
HBM JESD22-A114F Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 1.5
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78B Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP1T58GF Related Products

74AUP1T58GF 74AUP1T58GW 74AUP1T58GM 74AUP1T58
Description Low-power configurable gate with voltage-level translator Low-power configurable gate with voltage-level translator Low-power configurable gate with voltage-level translator Low-power configurable gate with voltage-level translator
Source Url Status Check Date 2013-06-14 00:00:00 2013-06-14 00:00:00 2013-06-14 00:00:00 -
Is it lead-free? Lead free Lead free Lead free -
Is it Rohs certified? conform to conform to conform to -
Maker NXP NXP NXP -
Parts packaging code SON SOT-363 SON -
package instruction 1 X 1 MM, 0.50 MM HEIGHT, PLASTIC, SOT-891, XSON-6 PLASTIC, SOT-363, SC-88, PACKAGE-6 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, XSON-6 -
Contacts 6 6 6 -
Reach Compliance Code compli compli compli -
series AUP/ULP/V AUP/ULP/V AUP/ULP/V -
JESD-30 code S-PDSO-N6 R-PDSO-G6 R-PDSO-N6 -
JESD-609 code e3 e3 e3 -
length 1 mm 2 mm 1.45 mm -
Load capacitance (CL) 30 pF 30 pF 30 pF -
Logic integrated circuit type LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT -
MaximumI(ol) 0.004 A 0.004 A 0.004 A -
Humidity sensitivity level 1 1 1 -
Number of functions 1 1 1 -
Number of terminals 6 6 6 -
Maximum operating temperature 125 °C 125 °C 125 °C -
Minimum operating temperature -40 °C -40 °C -40 °C -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code VSON TSSOP VSON -
Encapsulate equivalent code SOLCC6,.04,14 TSSOP6,.08 SOLCC6,.04,20 -
Package shape SQUARE RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE -
method of packing TAPE AND REEL TAPE AND REEL TAPE AND REEL -
Peak Reflow Temperature (Celsius) 260 260 260 -
power supply 2.5/3.3 V 2.5/3.3 V 2.5/3.3 V -
Prop。Delay @ Nom-Su 9.4 ns 9.4 ns 9.4 ns -
Certification status Not Qualified Not Qualified Not Qualified -
Schmitt trigger YES YES YES -
Maximum seat height 0.5 mm 1.1 mm 0.5 mm -
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V -
Minimum supply voltage (Vsup) 2.3 V 2.3 V 2.3 V -
Nominal supply voltage (Vsup) 3 V 3 V 3 V -
surface mount YES YES YES -
technology CMOS CMOS CMOS -
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE -
Terminal surface Tin (Sn) Tin (Sn) Tin (Sn) -
Terminal form NO LEAD GULL WING NO LEAD -
Terminal pitch 0.35 mm 0.65 mm 0.5 mm -
Terminal location DUAL DUAL DUAL -
Maximum time at peak reflow temperature 30 30 30 -
width 1 mm 1.25 mm 1 mm -
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