74AUP2G32GD datasheet, PDF - EEWORLD Datasheet

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74AUP2G32GD: DescriptionLow-power dual 2-input OR gate; Categorylogic logic; File Size78KB，17 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74AUP2G32GD Overview

Low-power dual 2-input OR gate

74AUP2G32GD Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SON
package instruction	3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8
Contacts	8
Reach Compliance Code	compli
series	AUP/ULP/V
JESD-30 code	R-PDSO-N8
JESD-609 code	e4
length	3 mm
Load capacitance (CL)	30 pF
Logic integrated circuit type	OR GATE
MaximumI(ol)	0.0017 A
Humidity sensitivity level	1
Number of functions	2
Number of entries	2
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VSON
Encapsulate equivalent code	SOLCC8,.11,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	1.2/3.3 V
Prop。Delay @ Nom-Su	23.7 ns
propagation delay (tpd)	23.7 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	2 mm

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74AUP2G32

Low-power dual 2-input OR gate

Rev. 03 — 8 January 2009

Product data sheet

1. General description

The 74AUP2G32 provides the dual 2-input OR function.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2. Features

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114E Class 3A exceeds 5 000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Low static power consumption; I

= 0.9

µA

(maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V

OFF

circuitry provides partial Power-down mode operation

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and

−40 °C

to +125

°C

74AUP2G32GD Related Products

	74AUP2G32GD	74AUP2G32DC	74AUP2G32GM	74AUP2G32	74AUP2G32GT
Description	Low-power dual 2-input OR gate	Low-power dual 2-input OR gate	Low-power dual 2-input OR gate	Low-power dual 2-input OR gate	Low-power dual 2-input OR gate
Is it Rohs certified?	conform to	conform to	conform to	-	conform to
Maker	NXP	NXP	NXP	-	NXP
Parts packaging code	SON	TSSOP	QFN	-	SON
package instruction	3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8	2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8	1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT902-1, QFN-8	-	1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8
Contacts	8	8	8	-	8
Reach Compliance Code	compli	compli	compli	-	compli
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	-	AUP/ULP/V
JESD-30 code	R-PDSO-N8	R-PDSO-G8	S-PQCC-N8	-	R-PDSO-N8
length	3 mm	2.3 mm	1.6 mm	-	1.95 mm
Load capacitance (CL)	30 pF	30 pF	30 pF	-	30 pF
Logic integrated circuit type	OR GATE	OR GATE	OR GATE	-	OR GATE
MaximumI(ol)	0.0017 A	0.0017 A	0.0017 A	-	0.0017 A
Humidity sensitivity level	1	1	1	-	1
Number of functions	2	2	2	-	2
Number of entries	2	2	2	-	2
Number of terminals	8	8	8	-	8
Maximum operating temperature	125 °C	125 °C	125 °C	-	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	VSON	VSSOP	VQCCN	-	VSON
Encapsulate equivalent code	SOLCC8,.11,20	TSSOP8,.12,20	LCC8,.06SQ,20	-	SOLCC8,.04,20
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	-	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH	CHIP CARRIER, VERY THIN PROFILE	-	SMALL OUTLINE, VERY THIN PROFILE
method of packing	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	-	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	-	260
power supply	1.2/3.3 V	1.2/3.3 V	1.2/3.3 V	-	1.2/3.3 V
Prop。Delay @ Nom-Su	23.7 ns	23.7 ns	23.7 ns	-	23.7 ns
propagation delay (tpd)	23.7 ns	23.7 ns	23.7 ns	-	23.7 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified
Schmitt trigger	NO	NO	NO	-	NO
Maximum seat height	0.5 mm	1 mm	0.5 mm	-	0.5 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	-	0.8 V
Nominal supply voltage (Vsup)	1.1 V	1.1 V	1.1 V	-	1.1 V
surface mount	YES	YES	YES	-	YES
technology	CMOS	CMOS	CMOS	-	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	-	AUTOMOTIVE
Terminal form	NO LEAD	GULL WING	NO LEAD	-	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	-	0.5 mm
Terminal location	DUAL	DUAL	QUAD	-	DUAL
Maximum time at peak reflow temperature	30	30	30	-	30
width	2 mm	2 mm	1.6 mm	-	1 mm

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