74AUP2G80_08 datasheet, PDF - EEWORLD Datasheet

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74AUP2G80_08: DescriptionLow-power dual D-type flip-flop; positive-edge trigger; File Size88KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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74AUP2G80_08 Overview

Low-power dual D-type flip-flop; positive-edge trigger

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74AUP2G80

Low-power dual D-type ﬂip-ﬂop; positive-edge trigger

Rev. 04 — 2 June 2008

Product data sheet

1. General description

The 74AUP2G80 provides the dual positive-edge triggered D-type ﬂip-ﬂop. Information on

the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock

transition for predictable operation.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing a damaging backﬂow current through the

device when it is powered down.

2. Features

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114E Class 3A exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Low static power consumption; I

= 0.9

µA

(maximum)

Latch-up performance exceeds 100 mA per JESD78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V

OFF

circuitry provides partial Power-down mode operation

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and

−40 °C

to +125

°C

74AUP2G80_08 Related Products

	74AUP2G80_08	74AUP2G80	74AUP2G80DC	74AUP2G80GM	74AUP2G80GD	74AUP2G80GT
Description	Low-power dual D-type flip-flop; positive-edge trigger	Low-power dual D-type flip-flop; positive-edge trigger	Low-power dual D-type flip-flop; positive-edge trigger	Low-power dual D-type flip-flop; positive-edge trigger	Low-power dual D-type flip-flop; positive-edge trigger	Low-power dual D-type flip-flop; positive-edge trigger
Is it Rohs certified?	-	-	conform to	conform to	conform to	conform to
Maker	-	-	NXP	NXP	NXP	NXP
Parts packaging code	-	-	TSSOP	QFN	SON	SON
package instruction	-	-	2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8	1.60 X 1.60 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-255, SOT902-2, QFN-8	3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8	1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8
Contacts	-	-	8	8	8	8
Reach Compliance Code	-	-	compli	compli	compli	compli
series	-	-	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V
JESD-30 code	-	-	R-PDSO-G8	S-PQCC-N8	R-PDSO-N8	R-PDSO-N8
length	-	-	2.3 mm	1.6 mm	3 mm	1.95 mm
Load capacitance (CL)	-	-	30 pF	30 pF	30 pF	30 pF
Logic integrated circuit type	-	-	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Su	-	-	70000000 Hz	70000000 Hz	70000000 Hz	70000000 Hz
MaximumI(ol)	-	-	0.0017 A	0.0017 A	0.0017 A	0.0017 A
Humidity sensitivity level	-	-	1	1	1	1
Number of digits	-	-	1	1	1	1
Number of functions	-	-	2	2	2	2
Number of terminals	-	-	8	8	8	8
Maximum operating temperature	-	-	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-	-	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	-	-	INVERTED	INVERTED	INVERTED	INVERTED
Package body material	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	VSSOP	HVQCCN	VSON	VSON
Encapsulate equivalent code	-	-	TSSOP8,.12,20	LCC8,.06SQ,20	SOLCC8,.11,20	SOLCC8,.04,20
Package shape	-	-	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR
Package form	-	-	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
method of packing	-	-	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	-	-	260	260	260	260
power supply	-	-	1.2/3.3 V	1.2/3.3 V	1.2/3.3 V	1.2/3.3 V
Prop。Delay @ Nom-Su	-	-	27.2 ns	27.2 ns	27.2 ns	27.2 ns
propagation delay (tpd)	-	-	27.2 ns	27.2 ns	27.2 ns	27.2 ns
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	-	1 mm	0.5 mm	0.5 mm	0.5 mm
Maximum supply voltage (Vsup)	-	-	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	-	-	0.8 V	0.8 V	0.8 V	0.8 V
Nominal supply voltage (Vsup)	-	-	1.1 V	1.1 V	1.1 V	1.1 V
surface mount	-	-	YES	YES	YES	YES
technology	-	-	CMOS	CMOS	CMOS	CMOS
Temperature level	-	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	-	-	GULL WING	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	-	-	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	-	-	DUAL	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	-	-	30	30	30	30
Trigger type	-	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	-	-	2 mm	1.6 mm	2 mm	1 mm
minfmax	-	-	510 MHz	510 MHz	510 MHz	510 MHz

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