74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Rev. 01 — 1 July 2009
Product data sheet
1. General description
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual
buffer/line driver with output enable circuitry.
The 74AUP2T1326 is designed for logic-level translation and combines the functions of
the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output
enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume
a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a
high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output
enable inputs.
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at
different voltages for positive and negative-going signals. The difference between the
positive voltage V
T+
and the negative voltage V
T−
is defined as the input hysteresis voltage
V
H
. The output enable inputs accept standard input signals and are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals
Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 1.1 V and 3.6 V making
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced
to V
CC(A)
and pins A, 2Y and 3Y are referenced to V
CC(B)
.
The device ensures low static and dynamic power consumption and is fully specified for
partial power down applications using I
OFF
. The I
OFF
circuitry disables the outputs,
preventing any damaging backflow current through the device when it is powered down.
2. Features
I
Wide supply voltage range:
N
V
CC(A)
: 1.1 V to 3.6 V; V
CC(B)
: 1.1 V to 3.6 V.
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 2A exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
I
I
I
I
I
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP2T1326GF
−40 °C
to +85
°C
XSON10U
Description
Version
plastic extremely thin small outline package; no leads; SOT1081-1
10 terminals; UTLP based; body 1 x 1.7 x 0.5 mm
Type number
4. Marking
Table 2.
Marking
Marking code
[1]
pf
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Type number
74AUP2T1326GF
5. Functional diagram
1OE
6
Rpd
8
1Y
2OE
7
Rpd
V
CC(A)
9
A
3
2
V
CC(B)
2Y
3Y
001aaj301
R
pd
= Internal pull-down resistor.
Fig 1.
Logic symbol
74AUP2T1326_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 1 July 2009
2 of 16
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
7. Functional description
Table 4.
Input
1OE
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
2OE
L
H
H
L
L
H
H
A
X
L
H
L
H
L
H
1Y
L
H
H
H
H
H
H
2Y
Z
Z
Z
L
H
L
H
3Y
Z
L
H
Z
Z
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+4.6
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
Unit
V
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
I
< 0 V
[1]
-50
−0.5
−50
−0.5
-
-
-50
−65
[2]
[1]
[2]
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CCO
T
amb
=
−40 °C
to +85
°C
[3]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
V
CCO
is the supply voltage associated with an output pin.
For XSON10U package: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC(A)
V
CC(B)
V
I
V
O
Recommended operating conditions
Parameter
supply voltage A
supply voltage B
input voltage
output voltage
[1]
Conditions
Min
1.1
1.1
0
0
Max
3.6
3.6
3.6
V
CCO
Unit
V
V
V
V
74AUP2T1326_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 1 July 2009
4 of 16
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Table 6.
Symbol
T
amb
∆t/∆V
Recommended operating conditions
…continued
Parameter
ambient temperature
input transition rise and fall rate
input A; V
CCI
= 1.1 V to 3.6 V
input nOE;
V
CCI
= 1.1 V to 3.6 V
[2]
[2]
Conditions
Min
−40
-
-
Max
+85
200
30
Unit
°C
ns/V
ms/V
[1]
[2]
V
CCO
is the supply voltage associated with an output pin.
V
CCI
is the supply voltage associated with an input pin.
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input
voltage
LOW-level
input
voltage
HIGH-level
output
voltage
Conditions
Min
input A;
V
CCI
= 1.65 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
input A;
V
CCI
= 1.65 V to 1.95 V
V
CCI
= 2.3 V to 2.7 V
V
I
= V
IL
or V
I
or V
I
= V
T+
or V
T−
I
O
=
−20 µA;
V
CCO
= 1.65 V to 2.7 V
I
O
=
−3
mA; V
CCO
= 1.65 V
I
O
=
−2.3
mA; V
CCO
= 2.3 V
I
O
=
−4.0
mA; V
CCO
= 2.3 V
V
OL
LOW-level
output
voltage
V
I
= V
IL
or V
I
or V
I
= V
T+
or V
T−
I
O
= 20
µA;
V
CCO
= 1.65 V to 2.7 V
I
O
= 3.0 mA; V
CCO
= 1.65 V
I
O
= 2.3 mA; V
CCO
= 2.3 V
I
O
= 4.0 mA; V
CCO
= 2.3 V
I
I
input
leakage
current
OFF-state
output
current
power-off
leakage
current
input A; V
I
= 0 V to 2.7 V;
V
CCI
= 1.65 V to 2.7 V
output 2Y, 3Y; V
I
= V
IH
or V
IL
;
V
O
= 0 V to 2.7 V;
V
CC(A)
= 1.65 V to 2.7 V;
V
CC(B)
= 1.65 V to 2.7 V
1Y; V
CC(A)
= 0 V;
V
O
= 0 V to 2.7 V;
V
CC(B)
= 1.65 V to 2.7 V
A, 2Y, 3Y; V
CC(B)
= 0 V;
V
I
or V
O
= 0 V to 2.7 V;
V
CC(A)
= 1.65 V to 2.7 V
74AUP2T1326_1
25
°C
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
0.35V
CCI
0.7
-
-
-
-
0.10
0.45
0.33
0.40
±0.1
[1][3]
−40 °C
to +85
°C
Min
0.65V
CCI
1.6
-
-
V
CCO
−
0.1
1.2
1.97
2.0
-
-
-
-
-
Max
-
-
0.35V
CCI
0.7
-
-
-
-
0.10
0.45
0.33
0.40
±0.5
Unit
0.65V
CCI
1.6
[1][3]
V
V
V
V
V
V
V
V
V
V
V
V
µA
V
IL
-
-
[2]
V
OH
V
CCO
−
0.1
1.2
1.97
2.0
[2]
-
-
-
-
[1]
-
I
OZ
-
-
±0.1
-
±0.5
µA
I
OFF
-
-
±0.2
-
±0.5
µA
-
-
±0.2
-
±0.5
µA
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 1 July 2009
5 of 16
Analog electronics
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