74F656A
Octal buffer/driver with parity; non-inverting; 3-state
Rev. 05 — 25 March 2010
Product data sheet
1. General description
The 74F656A is an octal buffer and line driver with parity generation/checking. The
74F656A can be used as memory address driver, clock driver and bus-oriented
transmitter/receiver. The inclusion of parity generation/checking improves PCB density.
2. Features
Combines 74F244 and 74F280A functions in one device
High impedance NPN base inputs for reduced input current (40
μA
in HIGH and LOW
states)
I
IL
= 20
μA
compared to 600
μA
in FAST family specification
For applications with high output drive and light bus loading
Non-inverting
3-state output sink capability I
OL
= 64 mA and source I
OH
= 15 mA
Inputs and outputs on separate sides simplifies board layout
Combined functions reduce part count and enhance system performance
Industrial temperature range available (−40
°C
to +85
°C)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
N74F656AD
I74F656AD
0
°C
to 70
°C
−40 °C
to +85
°C
Name
SO24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
Version
SOT137-1
Type number
NXP Semiconductors
74F656A
Octal buffer/driver with parity; non-inverting; 3-state
4. Functional diagram
2K
3
P3
3, 5, 6, 7, 8,
9, 10, 11, 12
3, 5, 6, 7, 8,
9, 10, 11, 12
1
2
≥1
EN4
[EVEN]
[ODD]
21
22
4
D0
3
1
2
23
PI
OE0
OE1
OE2
5
D1
6
D2
7
D3
8
D4
9
D5
10
D6
11
D7
ΣE
ΣO
21
22
23
4
5
6
7
8
9
10
11
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
4
20
19
18
17
16
15
14
13
001aal256
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
20
19
18
17
16
15
14
13
001aal255
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74F656A_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 March 2010
2 of 14
NXP Semiconductors
74F656A
Octal buffer/driver with parity; non-inverting; 3-state
PI
3
21
ΣE
ΣO
22
D0
4
20
Q0
D1
5
19
Q1
D2
6
18
Q2
D3
7
17
Q3
D4
8
16
Q4
D5
9
15
Q5
D6
10
14
Q6
D7
OE0
OE1
OE2
11
1
2
23
13
Q7
001aal253
Fig 3.
74F656A_5
Logic diagram
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 March 2010
3 of 14
NXP Semiconductors
74F656A
Octal buffer/driver with parity; non-inverting; 3-state
5. Pinning information
5.1 Pinning
74F656A
OE0
OE1
PI
D0
D1
D2
D3
D4
D5
1
2
3
4
5
6
7
8
9
24 V
CC
23 OE2
22
ΣO
21
ΣE
20 Q0
19 Q1
18 Q2
17 Q3
16 Q4
15 Q5
14 Q6
13 Q7
001aal254
D6 10
D7 11
GND 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
OE0
OE1
PI
D0 to D7
GND
Q0 to Q7
ΣE
ΣO
OE2
V
CC
[1]
Pin description
Pin
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
12
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
24
Description
output enable input (active LOW)
output enable input (active LOW)
parity input
data input
ground (0 V)
data output
even parity output
odd parity output
output enable input (active LOW)
supply voltage
750/106.7
750/106.7
750/106.7
1.0/0.033
15 mA/64 mA
15 mA/64 mA
15 mA/64 mA
20
μA/20 μA
Unit load
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
2.0/0.066
Load value
[1]
HIGH/LOW
20
μA/20 μA
20
μA/20 μA
20
μA/20 μA
40
μA/40 μA
One FAST Unit Load (UL) is defined as 20
μ
A in HIGH state, 0.6
μ
A in LOW state.
74F656A_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 March 2010
4 of 14
NXP Semiconductors
74F656A
Octal buffer/driver with parity; non-inverting; 3-state
6. Functional description
6.1 Function table
Table 3.
Input
OE0
L
L
H
X
X
[1]
Function selection
[1]
Output
OE1
L
L
X
H
X
OE2
L
L
X
X
H
Dn
L
H
X
X
X
Qn
L
H
Z
Z
Z
disabled
transparent
Status
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Table 4.
Inputs
Function parity outputs
[1]
State
H
H
H
Parity output
ΣE
ΣO
L
H
Z
H
L
Z
Even number of inputs
(0, 2, 4, 6, 8)
Odd number of inputs
(1, 3, 5, 7, 9)
Any OEn
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
74F656A_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 March 2010
5 of 14
京公网安备 11010802033920号
EEWORLD
