Commercial/Industrial
PA7572 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (f
MAX
)
-
Industrial grade available for 4.5 to 5.5V V
CC
and -40
to +85 °C temperatures
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
CMOS Electrically Erasable Technology
-
Reprogrammable in 40-pin DIP,
44-pin PLCC and TQFP packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
General Description
The PA7572 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7572 offers a
versatile logic array architecture with 24 I/O pins, 14 input
pins and 60 registers/latches (24 buried logic cells, 12 input
registers/latches, 24 buried I/O registers/latches). Its logic
array implements 100 sum-of-products logic functions
divided into two groups each serving 12 logic cells. Each
group shares half (60) of the 120 product-terms available.
The PA7572’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7572 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. The
PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
and 66.6MHz (f
MAX
) at moderate power consumption
140mA (100mA typical). Packaging includes 40-pin DIP
and 44-pin PLCC (see Figure 1). ICT and popular third-
party
development
tool
manufacturers
provide
development and programming support for the PA7572.
Figure 1. Pin Configuration
I/C LK1
VC C
I/O
I
Figure 2. Block Diagram
VC C
I
I
I
I/O
D IP (60 0 m il)
I/C LK1
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VC C
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/C LK2
I/O
I/O
PLCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
2 Inp u t/
G lo b a l C lo c k P in s
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
I/O
I
I
I
I/C LK2
I
I
I
I/O
GND
GND
I
I
G lo b a l
C e lls
1 2 In p u t P ins
In p ut
C e lls
(IN C )
2
1 2 4 (6 2 X 2)
A rray In p u ts
true an d
c o m p lem e n t
I/O
C e lls
(IO C )
B u rie d
lo g ic
L o g ic
fu n c tio n s
to I/O c e lls
2 4 I/O P ins
12
24
24
I/CLK
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
GN D
Logic C ontrol Cells
I/O Cells
Input C ells
Global C ells
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
Lo gic
A rray
A
B
C
D
I/C LK1
VC C
VC C
I/O
I
I
I
I
I/O
L o gic
C o n tro l
C e lls
(L C C )
24
I
I
24
4 s um te rm s
5 p ro d u c t te rm s
fo r G lob a l C e lls
9 6 s u m term s
(fou r p er L C C )
2 4 L o gic C o n tro l C e lls
u p to 3 o utp ut fun c tio ns pe r c e ll
(7 2 tota l o u tp u t fu nc tio n s
p o s s ib le )
TQ FP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
5
6
7
8
9
30
29
28
27
26
25
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
I/O
I
I
I
I
I
I/C LK2
GND
GND
I
I/O
08-15 -0 01A
PA 7572
08-15-002A
I/CLK 2
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Commercial/Industrial
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7572 PEEL™ Array, 62 inputs are
available into the array from the I/O cells, inputs cells and
input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7572 PEEL™ Arrays contains 124 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
products functions provided to the logic cells can be used for
clocks, resets, presets and output enables instead of just
simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From G lobal C ell
F rom
IO Cells
(IO C ,INC ,
I/CLK)
62 A rray Inputs
S ys tem C lock
P reset
R egT ype R eset
On /O ff
MUX
P
D,T,J
Q
To
A rray
F rom
Logic
Control
Cells
(LC C)
MUX
K
REG
R
A
From
A rray
To
G lobal
Cells
125 P roduct
T erm s
B
C
D
MUX
To
I/O
C ell
To
Logic C ontrol
Cells
(LC C)
08 -15 -00 4A
Figure 4. Logic Control Cell Block Diagram
08-15-003A
P A 757 2 Log ic A rray
100 S um Term s
Figure 3. PA7572 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as com-
monly found in other CPLDs. Product term sharing ensures
that product-terms are used where they are needed and
not left unutilized or duplicated. Secondly, the sum-of-
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
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Commercial/Industrial
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
P
D R e g is te r
Q = D after c loc k ed
D
Q
B es t for s torage, s im ple c ounters ,
s hifters and s tate m ac hines w ith
few hold (loop) c onditions .
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one combinatorial and the third, an output
enable, or an additional buried logic function. The multi-
function PEEL™ Array logic cells are equivalent to two or
three macrocells of other PLDs, which have one output per
cell. They also allow registers to be truly buried from I/O pins
without limiting them to input-only (see Figure 8 & Figure 9).
F rom G lobal C ell
Input C ell C lock
R
T
P
Q
T R e g is te r
Q toggles w hen T = 1
Q holds w hen T = 0
R
B es t for w ide binary c ounters (s av es
produc t term s ) and s tate m ac hines
w ith m any hold (loop) c onditions .
REG/
L atc h
Q
M UX
J
P
Q
K
J K R e g is te r
Q toggles w hen J /K = 1/1
Q holds w hen J /K = 0/0
Q = 1
w hen J /K = 1/0
Q = 0
w hen J /K = 0/1
Input
Input C ell (IN C )
Input
To
A rray
R
C om bines features of both D and T
regis ters .
08-15-005A
F rom G lobal C ell
Input C ell C lock
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 9).
REG/
L atc h
Q
To
A rray
Input
M UX
M UX
F rom
Logic
C ontrol
C ell
A ,B ,C
or
Q
M UX
I/O P in
M UX
D
1 0
I/O C ell (IO C )
0 8-1 5 -00 6 A
Figure 6. Input and I/O Cell Block Diagrams
D
Q
IO C /IN C R e g is te r
Q = D after ris ing edge of c loc k
holds until next ris ing edge
L
Q
IO C /IN C L a tc h
Q = L w hen c loc k is high
holds v alue w hen c loc k is low
Multiple Outputs Per Logic Cell
08-15-007A
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Figure 7. IOC/INC Register Configurations
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Commercial/Industrial
Input Cells (INC)
Input cells (INC) are included on dedicated input pins. The
block diagram of the INC is shown in Figure 6. Each INC
consists of a multiplexer and a register/transparent latch,
which can be clocked from various sources selected by the
global cell (see Figure 7). The register is rising edge
clocked. The latch is transparent when the clock is high
and latched on the clock’s falling edge. The register/ latch
can also be bypassed for a non-registered input.
Global Cells
The global cells, shown in Figure 10, are used to direct global
clock signals and/or control terms to the LCCs, IOCs and
INCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for INC and IOC
clocks enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has its
own polarity control. The global cell for LCCs includes sum-
of-products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to save
product terms for loadable counters and state machines (see
Figure 11). The PA7572 provides two global cells that divide
the LCC and IOCs into groups, A and B. Half of the LCCs and
IOCs use global cell A, half use global cell B. This means that
two high-speed global clocks can be used among the LCCs.
C LK 1
C LK 2
MUX
P C LK
IN C C loc k s
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. The PA7572 allows the use of SUM-D as
a feedback to the array when the I/O pin is a dedicated
output. This allows for additional buried registers and logic
paths. (See Figure 8 and Figure 9).
G lobal C ell: IN C
G roup A & B
C LK 1
C LK 2
Q
D
MUX
LC C C loc k s
MUX
P C LK
IO C C loc k s
Input w ith optional
regis ter/latch
I/O
R eg-Type
P res et
LC C R eg-Type
LC C P res ets
LC C R es ets
I/O w ith
independent
output enable
1
A
B
C
D
OE
08-15-008A
D
Q
R es et
G lo bal C ell: LC C & IO C
08-15-010A
2
Figure 10. Global Cells
R eg-Type from G lob al C ell
Figure 8. LCC & IOC With Two Outputs
R e g is te r T y p e C h a n g e F e a tu re
D
Q
D
P
Q
Buried register or
logic paths
O utput
R
G lobal C ell c an dynam ic ally c hange us er-
s elec ted LCC regis ters from D to T or from D
to J K . This s av es produc t term s for loadable
c ounters or s tate m ac hines . U se as D regis ter
to load, use as T or J K to c ount. Tim ing
allow s dynam ic operation.
1
A
B
C
D
2
3
D
Q
T
P
E x a m p le :
P roduc t term s for 10 bit loadable binary c ounter
Q
D us es 57 produc t term s (47 c ount, 10 load)
T us es 30 produc t term s (10 c ount, 20 load)
D /T us es 20 produc t term s (10 count, 10 load)
08-15-011 A
R
08-15-0 09A
Figure 9. LCC & IOC With Three Outputs
Figure 11. Register Type Change Feature
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Commercial/Industrial
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
ICT and manufacturers of popular development tools. ICT
offers the powerful PLACE Development Software (free to
qualified PLD designers).
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
internal signals to be simulated and analyzed via a
waveform display.(See Figure 12, Figure 13, Figure 14)
unexpected changes to be made quickly and without
waste. Programming of PEEL™ Arrays is supported by
many popular third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 13. PLACE LCC and IOC Screen
Figure 12. PLACE Architectural Editor
PEEL™ Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT’s
PEEL™ Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEEL™ Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE-
reprogrammability is also useful for production, allowing
Figure 14. PLACE Simulator Screen
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