HD74ALVC162835A
18-bit Universal Bus Driver with 3-state Outputs
ADE-205-294C (Z)
Rev. 3
Oct. 2001
Description
The HD74ALVC162835A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode
when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high
transition of CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include series dumping resistors to reduce overshoot
and undershoot.
Features
•
Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
•
VCC = 2.3 V to 3.6 V
•
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
•
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
•
High output current ±12 mA (@VCC = 3.0 V)
•
All outputs have series dumping resistors, so no external resistors are required
•
tpd (CLK to Y) = 3.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 50 pF, Ta = 0 to 85°C)
•
tpd (CLK to Y) = 2.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 30 pF, Ta = 0 to 85°C)
•
Package type
Package type
TSSOP-56pin
TVSOP-56pin
Package code
TTP-56DAV
TTP-56DBV
Package suffix
T
N
Taping code
EL(1000pcs / Reel)
EL(1000pcs / Reel)
HD74ALVC162835A
Function Table
Inputs
OE
H
L
L
L
L
L
H:
L:
X:
Z:
↑
:
Note:
LE
X
H
H
L
L
L
CLK
X
X
X
↑
↑
L or H
A
X
L
H
L
H
X
Output Y
Z
L
H
L
H
Y
0
*1
High level
Low level
Immaterial
High impedance
Low to high transition
1. Output level before the indicated steady-state input conditions were established.
Rev.3, Oct. 2001, page 2 of 17
HD74ALVC162835A
Pin Arrangement
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
V
CC
7
Y4 8
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
V
CC
22
Y16 23
Y17 24
GND 25
Y18 26
OE
27
LE 28
(Top view)
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 V
CC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 V
CC
34 A16
33 A17
32 GND
31 A18
30 CLK
29 GND
Rev.3, Oct. 2001, page 3 of 17
HD74ALVC162835A
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range
Input clamp current
Output clamp current
Continuous output current
V
CC
, GND current / pin
Maximum power dissipation
*3
at Ta = 55°C (in still air)
Storage temperature range
*1
*1, 2
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
–50
±50
±50
±100
1
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
W
°C
Conditions
Output voltage range
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
TSSOP
TVSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output
clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150°C and board
trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High-level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low-level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating free-air temperature
•t/•v
Ta
0
–40
Max
3.6
V
CC
V
CC
–6
–8
–12
6
8
12
10
85
ns/V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused or floating control pins must be held high or low.
Rev.3, Oct. 2001, page 4 of 17
HD74ALVC162835A
Logic Diagram
OE
CLK
LE
A1
27
30
28
54
1D
C1
CLK
3
Y1
To seventeen other channels
Rev.3, Oct. 2001, page 5 of 17
Embedded System
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