74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Rev. 05 — 13 July 2009
Product data sheet
1. General description
The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output
pulse width control by three methods:
1. The basic pulse is programmed by selection of an external resistor (R
EXT
) and
capacitor (C
EXT
).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
3. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in the function table.
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered
via the reset input.
2. Features
I
I
I
I
I
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt-trigger action on all inputs except for the reset input
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC123N
74HCT123N
74HC123D
74HCT123D
74HC123DB
74HCT123DB
74HC123PW
74HCT123PW
74HC123BQ
−40 °C
to +125
°C
DHVQFN16
−40 °C
to +125
°C
TSSOP16
−40 °C
to +125
°C
SSOP16
−40 °C
to +125
°C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
SOT109-1
SOT338-1
SOT403-1
SOT763-1
−40 °C
to +125
°C
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
4. Functional diagram
14
15
S
1A
1
T
2
Q
4
Q
1CEXT
1REXT/CEXT
13
1Q
1Q
1B
RD
3
6
7
S
2CEXT
1RD
2REXT/CEXT
2A
9
T
10
Q
5
2Q
Q
12
2Q
2B
RD
11
001aaa610
2RD
Fig 1.
Functional diagram
74HC_HCT123_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 13 July 2009
2 of 24
NXP Semiconductors
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
14
15
1
2
1CEXT 14
2CEXT
6
3
CX
RCX
&
4
R
13
1REXT/CEXT
15
2REXT/CEXT
S
1 1A
9 2A
2 1B
10 2B
3 1RD
11 2RD
T
Q
1Q
4
2Q 12
11
mna515
7
6
CX
RCX
&
12
R
mna516
Q
1Q 13
2Q 5
7
9
10
5
RD
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
nREXT/CEXT
V
CC
nRD
R
CL
R
CL
nQ
nQ
V
CC
V
CC
R
CL
nA
CL
CL
nB
R
mna518
Fig 4.
74HC_HCT123_5
Logic diagram
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 13 July 2009
3 of 24
NXP Semiconductors
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
74HC123
terminal 1
index area
1B
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
9
001aaa698
74HC123
74HCT123
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
2A
9
V
CC(1)
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
1
1A
2A
001aaf046
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 5.
Pin configuration for DIP16, SO16, SSOP16
and TSSOP16
Fig 6.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
2A
2B
2RD
2Q
1Q
1CEXT
1REXT/CEXT
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
negative-edge triggered input 1
positive-edge triggered input 1
direct reset LOW and positive-edge triggered input 1
active LOW output 1
active HIGH output 2
external capacitor connection 2
external resistor and capacitor connection 2
ground (0 V)
negative-edge triggered input 2
positive-edge triggered input 2
direct reset LOW and positive-edge triggered input 2
active LOW output 2
active HIGH output 1
external capacitor connection 1
external resistor and capacitor connection 1
supply voltage
74HC_HCT123_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 13 July 2009
4 of 24
NXP Semiconductors
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
6. Functional description
Table 3.
Input
nRD
L
X
X
H
H
↑
[1]
Function table
[1]
Output
nA
X
H
X
L
↓
L
nB
X
X
L
↑
H
H
nQ
L
L
[2]
L
[2]
nQ
H
H
[2]
H
[2]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition;
= one HIGH level output pulse;
= one LOW level output pulse.
[2]
If the monostable was triggered before this condition was established, the pulse will continue as programmed.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 package
SSOP16 package
TSSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
°C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
°C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
°C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
°C.
[1]
[2]
[3]
[3]
[4]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
except for pins nREXT/CEXT;
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
Min
−0.5
-
-
-
-
-
−65
-
-
-
-
-
Max
+7
±20
±20
±25
50
−50
+150
750
500
500
500
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
mW
mW
74HC_HCT123_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 13 July 2009
5 of 24
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