INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4024
7-stage binary ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4024 are high-speed Si-gate CMOS
devices and are pin compatible with the “4024” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4024 are 7-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and seven fully buffered parallel
outputs (Q
0
to Q
6
).
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4024
The counter advances on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
APPLICATIONS
•
Frequency dividing circuits
•
Time delay circuits
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay CP to Q
0
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
90
3.5
25
HCT
14
70
3.5
27
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
7-stage binary ripple counter
PIN DESCRIPTION
PIN NO.
1
2
7
8, 10, 13
14
SYMBOL
CP
MR
GND
n.c.
V
CC
NAME AND FUNCTION
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
parallel outputs
ground (0 V)
not connected
positive supply voltage
74HC/HCT4024
12, 11, 9, 6, 5, 4, 3 Q
0
to Q
6
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
7-stage binary ripple counter
FUNCTION TABLE
INPUTS
CP
↑
↓
X
Notes
MR
L
L
H
74HC/HCT4024
OUTPUTS
Q
n
no change
count
L
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH clock transition
↓ =
HIGH-to-LOW clock transition
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
7-stage binary ripple counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+125 −40
to
+125
max.
265
53
45
300
60
51
120
24
20
110
22
19
120
24
20
120
24
20
75
15
13
4.0
20
24
74HC/HCT4024
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
propagation delay
MR to Q
0
propagation delay
Q
n
to Q
n+1
output transition time
47
17
14
63
23
18
25
9
7
19
7
6
80
16
14
80
16
14
50
10
9
6.0
30
35
17
6
5
22
8
6
6
2
2
27
82
98
175
35
30
200
40
34
80
16
14
75
15
13
100
20
17
100
20
17
65
13
11
4.8
24
28
220
44
37
250
50
43
100
20
17
95
19
16
t
PHL
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
master reset pulse width
HIGH
removal time
MR to CP
maximum clock pulse
frequency
ns
Fig.6
t
W
ns
Fig.6
t
rem
ns
Fig.6
f
max
MHz
Fig.6
December 1990
5
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