74LVTH16374ADGG datasheet, PDF

Datasheet> All Categories > logic> logic> 74LVTH16374ADGG

74LVTH16374ADGG: Description3.3 V 16-bit edge-triggered D-type flip-flop; 3-state; Categorylogic logic; File Size157KB，19 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

Download Datasheet Parametric Compare View All

74LVTH16374ADGG Overview

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74LVTH16374ADGG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP
package instruction	6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48
Contacts	48
Reach Compliance Code	compli
series	LVT
JESD-30 code	R-PDSO-G48
length	12.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
Maximum Frequency@Nom-Su	150000000 Hz
MaximumI(ol)	0.064 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	5 ns
propagation delay (tpd)	5.6 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	6.1 mm

Preview

Download Datasheet

View All

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Rev. 07 — 22 March 2010

Product data sheet

1. General description

The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for

operation at 3.3 V.

This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state

outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the

positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic

levels set up at the nDn inputs.

2. Features and benefits

16-bit edge-triggered flip-flop

3-state buffers

Output capability: +64 mA and

−32

TTL input and output switching levels

Input and output interface capability to systems at 5 V supply

Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

Live insertion and extraction permitted

Power-up reset

Power-up 3-state

No bus current loading when output is tied to 5 V bus

Latch-up protection:

JESD78B Class II exceeds 500 mA

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

74LVTH16374ADGG Related Products

	74LVTH16374ADGG	74LVT16374A	74LVT16374ADGG	74LVTH16374A	74LVTH16374ABQ
Description	3.3 V 16-bit edge-triggered D-type flip-flop; 3-state	3.3 V 16-bit edge-triggered D-type flip-flop; 3-state	3.3 V 16-bit edge-triggered D-type flip-flop; 3-state	3.3 V 16-bit edge-triggered D-type flip-flop; 3-state	3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Is it Rohs certified?	conform to	-	conform to	-	conform to
Maker	NXP	-	NXP	-	NXP
Parts packaging code	TSSOP	-	TSSOP	-	QFN
package instruction	6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48	-	6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48	-	4 X 6 MM, 0.50 MM HEIGHT, PLASTIC, SOT1134-1, HQFN-60
Contacts	48	-	48	-	60
Reach Compliance Code	compli	-	compli	-	compli
series	LVT	-	LVT	-	LVT
JESD-30 code	R-PDSO-G48	-	R-PDSO-G48	-	R-PBCC-B60
length	12.5 mm	-	12.5 mm	-	6 mm
Load capacitance (CL)	50 pF	-	50 pF	-	50 pF
Logic integrated circuit type	BUS DRIVER	-	BUS DRIVER	-	BUS DRIVER
Humidity sensitivity level	1	-	1	-	2
Number of digits	8	-	8	-	8
Number of functions	2	-	2	-	2
Number of ports	2	-	2	-	2
Number of terminals	48	-	48	-	60
Maximum operating temperature	85 °C	-	85 °C	-	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-	-40 °C
Output characteristics	3-STATE	-	3-STATE	-	3-STATE
Output polarity	TRUE	-	TRUE	-	TRUE
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TSSOP	-	TSSOP	-	HVBCC
Package shape	RECTANGULAR	-	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)	5.6 ns	-	5.6 ns	-	5.6 ns
Certification status	Not Qualified	-	Not Qualified	-	Not Qualified
Maximum seat height	1.2 mm	-	1.2 mm	-	0.5 mm
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	2.7 V	-	2.7 V	-	2.7 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V	-	3.3 V
surface mount	YES	-	YES	-	YES
technology	BICMOS	-	BICMOS	-	BICMOS
Temperature level	INDUSTRIAL	-	INDUSTRIAL	-	INDUSTRIAL
Terminal form	GULL WING	-	GULL WING	-	BUTT
Terminal pitch	0.5 mm	-	0.5 mm	-	0.5 mm
Terminal location	DUAL	-	DUAL	-	BOTTOM
width	6.1 mm	-	6.1 mm	-	4 mm

Recommended Resources

Multiple switches control a lamp circuit b

Common Mode Volume and Tone Control Circuit

Green Island Feng brand variable speed ventilation fan circuit diagram

Simple DA converter

Two-stage differential amplifier circuit

Voice control delay power saving switch

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components