8Mx8/4Mx16/2Mx32, 20 - 45ns, PGA
30A128-18
A
64 Megabit High Speed CMOS SRAM
DPS2MK32MKV3
PRELIMINARY
DESCRIPTION:
The DPS2MK32MKV3 ‘’VERSA-STACK’’ module is a
revolutionary new high speed memory subsystem using
Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC) mounted on a co-fired ceramic substrate. It
offers 64 Megabits of SRAM in a package envelope of 1.190 x
1.190 x 0.660 inches.
The DPS2MK32MKV3 contains sixteen individual 512K x 8
SRAMs, packaged in their own hermetically sealed SLCCs
making the module suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a
higher board density of memory than available with
conventional through-hole, surface mount, module, or hybrid
techniques.
FEATURES:
•
Organizations Available:
READ:
WRITE:
FUNCTIONAL BLOCK DIAGRAM
2 Meg x 32
2 Meg x 32, 4 Meg x 16
or 8 Meg x 8
•
Access Times:
20*, 25, 35, 45ns
•
Fully Static Operation
- No clock or refresh required
•
Low Power Dissipation
•
Single +5V Power Supply,
•
•
•
•
±10%
Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Current
66-Pin PGA Special ‘’VERSA-STACK’’
Package with Compatable Footprint
*
Commercial and Industrial only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O31
CE0 - CE3
WE0 - WE3
OE
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Low Chip Enables
Write Enables
Output Enable
Power (+5V)
Ground
No Connect
30A128-18
REV. A
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS2MK32MKV3
PRELIMINARY
TRUTH TABLE
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
Supply
I/O Pin Current
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
2
V
IL
Input LOW Voltage -0.5
0.8
V
M -55 +25 +125
Operating
o
C
T
A
I
-40 +25
+85
Temperature
C
0 +25
+70
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4
V
3
CAPACITANCE
4
: T
A
= 25
°
C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
150
45
45
150
45
Unit
Condition
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
Value
Unit
-65 to +150
°C
-55 to +125
°C
-0.5 to +7.0
°C
-0.5 to V
DD
+0.5 V
pF
V
IN2
= 0V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3V)
Data Retention
Supply Current (2V)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V,
V
IN
≥
V
DD
-0.2V or V
IN
≤
+0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V,
V
IN
≥
V
DD
-0.2V or V
IN
≤
+0.2V
I
OUT
= 8.0mA
I
OUT
= -4.0mA
Typ.
(†)
-
-
740
16.0
320
2.4
1.6
-
-
2.4
C
Min.
Max.
Min.
I
Max.
Min.
M
Max.
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
-80
-40
+80
+40
1400
160
960
8.0
4.8
0.4
-80
-40
+80
+40
1440
160
960
16.0
12.8
0.4
-80
-40
+80
+40
1440
240
960
32.0
28.8
0.4
2.4
2.4
† Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
Data Retention AC Characteristics
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
8
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
30A128-18
REV. A
2
Dense-Pac Microsystems, Inc.
PRELIMINARY
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
Load
1
2
C
L
30pF
5pF
DPS2MK32MKV3
OUTPUT LOAD
Parameters Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
Figure 1.
Output Load
* Including Probe and Jig
Capacitance.
V
DD
4.5V
2.3V
V
DR1
DATA RETENTION WAVEFORM:
CE Controlled.
+5V
480Ω
D
OUT
C
L
*
255Ω
CE
0V
CE
≥
V
DD
-0.2V
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
10
3
0
0
4
8
8
25
25
25
12
3
0
0
5
10
10
30
30
30
15
3
0
0
5
15
15
35
35
35
20
3
0
0
5
20
20
45
45
45
25
3
0
0
5
25
25
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time **
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
13
13
0
13
0
0
9
0
3
8
25
15
15
0
15
0
0
10
0
3
10
30
20
20
0
20
0
0
12
0
3
12
35
25
25
0
25
0
0
15
0
3
15
45
35
35
0
35
0
0
20
0
3
20
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
30A128-18
REV. A
3
DPS2MK32MKV3
PRELIMINARY
Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
4
30A128-18
REV. A
Dense-Pac Microsystems, Inc.
PRELIMINARY
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
DPS2MK32MKV3
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1. All voltages are with respect to V
SS
.
2. -2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V at DC
level).
3. Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
30A128-18
REV. A
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of
±500mV
from steady state
voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the
output state,and input signals of opposite phase to the outputs
must not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
5
Analog electronics
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