5962-9212201MXA datasheet, PDF

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5962-9212201MXA: DescriptionError Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144; Categorylogic logic; File Size1MB，38 Pages; ManufacturerIDT (Integrated Device Technology)

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5962-9212201MXA Overview

Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144

5962-9212201MXA Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Parts packaging code	PGA
package instruction	PGA,
Contacts	144
Reach Compliance Code	unknown
Other features	FEED THROUGH EDAC; 64 BIT GENERATE MODE; BUILT IN DIAGNOSTICS; ON CHIP PIPELINING; BYTE CONTROL
series	49C
JESD-30 code	S-CPGA-P144
JESD-609 code	e0
length	39.9923 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits	32
Number of functions	1
Number of terminals	144
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
propagation delay (tpd)	18 ns
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	4.699 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	39.9923 mm

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5962-9212201MXA Related Products

	5962-9212201MXA	5962-9212202MXA
Description	Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144	Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144
Parts packaging code	PGA	PGA
package instruction	PGA,	PGA,
Contacts	144	144
Reach Compliance Code	unknown	unknown
Other features	FEED THROUGH EDAC; 64 BIT GENERATE MODE; BUILT IN DIAGNOSTICS; ON CHIP PIPELINING; BYTE CONTROL	FEED THROUGH EDAC; 64 BIT GENERATE MODE; BUILT IN DIAGNOSTICS; ON CHIP PIPELINING; BYTE CONTROL
series	49C	49C
JESD-30 code	S-CPGA-P144	S-CPGA-P144
JESD-609 code	e0	e0
length	39.9923 mm	39.9923 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	ERROR DETECTION AND CORRECTION CIRCUIT	ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits	32	32
Number of functions	1	1
Number of terminals	144	144
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Output characteristics	3-STATE	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
propagation delay (tpd)	18 ns	20 ns
Certification status	Not Qualified	Not Qualified
Filter level	MIL-STD-883	MIL-STD-883
Maximum seat height	4.699 mm	4.699 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	TIN LEAD	TIN LEAD
Terminal form	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR
width	39.9923 mm	39.9923 mm

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