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5962-9212202MXA

Description
Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144
Categorylogic    logic   
File Size1MB,38 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

5962-9212202MXA Overview

Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144

5962-9212202MXA Parametric

Parameter NameAttribute value
Parts packaging codePGA
package instructionPGA,
Contacts144
Reach Compliance Codeunknown
Other featuresFEED THROUGH EDAC; 64 BIT GENERATE MODE; BUILT IN DIAGNOSTICS; ON CHIP PIPELINING; BYTE CONTROL
series49C
JESD-30 codeS-CPGA-P144
JESD-609 codee0
length39.9923 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeERROR DETECTION AND CORRECTION CIRCUIT
Number of digits32
Number of functions1
Number of terminals144
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
propagation delay (tpd)20 ns
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height4.699 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width39.9923 mm
Base Number Matches1

5962-9212202MXA Related Products

5962-9212202MXA 5962-9212201MXA
Description Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144 Error Detection And Correction Circuit, 49C Series, 32-Bit, CMOS, CPGA144, CAVITY-UP, PGA-144
Parts packaging code PGA PGA
package instruction PGA, PGA,
Contacts 144 144
Reach Compliance Code unknown unknown
Other features FEED THROUGH EDAC; 64 BIT GENERATE MODE; BUILT IN DIAGNOSTICS; ON CHIP PIPELINING; BYTE CONTROL FEED THROUGH EDAC; 64 BIT GENERATE MODE; BUILT IN DIAGNOSTICS; ON CHIP PIPELINING; BYTE CONTROL
series 49C 49C
JESD-30 code S-CPGA-P144 S-CPGA-P144
JESD-609 code e0 e0
length 39.9923 mm 39.9923 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type ERROR DETECTION AND CORRECTION CIRCUIT ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits 32 32
Number of functions 1 1
Number of terminals 144 144
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C
Output characteristics 3-STATE 3-STATE
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code PGA PGA
Package shape SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY
propagation delay (tpd) 20 ns 18 ns
Certification status Not Qualified Not Qualified
Filter level MIL-STD-883 MIL-STD-883
Maximum seat height 4.699 mm 4.699 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount NO NO
technology CMOS CMOS
Temperature level MILITARY MILITARY
Terminal surface TIN LEAD TIN LEAD
Terminal form PIN/PEG PIN/PEG
Terminal pitch 2.54 mm 2.54 mm
Terminal location PERPENDICULAR PERPENDICULAR
width 39.9923 mm 39.9923 mm
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