DSPB56007FJ88 datasheet, PDF - EEWORLD Datasheet

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DSPB56007FJ88: DescriptionIC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size631KB，83 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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DSPB56007FJ88 Overview

IC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC

DSPB56007FJ88 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	QFP
package instruction	QFP,
Contacts	80
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	18
barrel shifter	NO
boundary scan	NO
maximum clock frequency	88 MHz
External data bus width	8
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQFP-G80
length	14 mm
low power mode	YES
Number of terminals	80
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Maximum seat height	2.45 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	HCMOS
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document by:

DSP56007/D

DSP56007

SYMPHONY

™

AUDIO DSP FAMILY

24-BIT DIGITAL SIGNAL PROCESSORS

Motorola designed the Symphony

™

family of high-performance, programmable Digital Signal

Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,

ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by

Motorola for integration into products like audio/video receivers, televisions, and automotive

sound systems with such user-developed features as digital equalization and sound field

processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit

Digital Signal Processor core, program and data memories, various peripherals optimized for

audio, and support circuitry. As illustrated in

Figure 1

, the DSP56000 core family compatible

DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial

Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated

I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE

™

) port. The

DSP56007 has significantly more on-chip memory than the DSP56004.

Freescale Semiconductor, Inc...

General

Purpose

Input/

Output

Serial

Audio

Interface

(SAI)

Serial

Host

Interface

(SHI)

External

Memory

16-Bit Bus

24-Bit Bus

Interface

(EMI)

Program

Memory*

X Data

Memory*

Y Data

Memory*

24-Bit

DSP56000

Core

Internal

Data

Bus

Switch

Address

Generation

Unit

PAB

XAB

YAB

GDB

PDB

XDB

YDB

OnCE

Port

Clock

Gen.

Interrupt

Control

PLL

Program

Address

Decode

Generator

Controller

Program Control Unit

Data ALU

24 + 56

→

56-Bit MAC

Two 56-Bit Accumulators

IRQA, IRQB, NMI, RESET

Refer to Table 1 for memory configurations.

AA0248

Figure 1

DSP56007 Block Diagram

For More Information On This Product,

Go to: www.freescale.com

DSPB56007FJ88 Related Products

	DSPB56007FJ88	DSPE56007FJ50	DSPE56007FJ66	DSPE56007FJ88	DSPB56007FJ66	DSPB56007FJ50
Description	IC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC	8-BIT, 50MHz, OTHER DSP, PQFP80, 14 X 14 MM, 2.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-80	IC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC	IC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC	IC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC	IC,DSP,24-BIT,CMOS,QFP,80PIN,PLASTIC
Maker	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	QFP,	QFP,	QFP,	QFP,	QFP,	QFP,
Contacts	80	80	80	80	80	80
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknow
Address bus width	18	18	18	18	18	18
barrel shifter	NO	NO	NO	NO	NO	NO
boundary scan	NO	NO	NO	NO	NO	NO
maximum clock frequency	88 MHz	50 MHz	66 MHz	88 MHz	66 MHz	50 MHz
External data bus width	8	8	8	8	8	8
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80
length	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
low power mode	YES	YES	YES	YES	YES	YES
Number of terminals	80	80	80	80	80	80
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	QFP	QFP	QFP	QFP	QFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.45 mm	2.45 mm	2.45 mm	2.45 mm	2.45 mm	2.45 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
ECCN code	3A001.A.3	3A001.A.3	-	3A001.A.3	3A001.A.3	3A001.A.3

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